Wing-Kai Chow

According to our database1, Wing-Kai Chow authored at least 22 papers between 2010 and 2022.

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Timeline

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Bibliography

2022
Pin-Accessible Legalization for Mixed-Cell-Height Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2019
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2018
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ISPD 2018 Initial Detailed Routing Contest and Benchmarks.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Routability-driven and fence-aware legalization for mixed-cell-height circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Timing driven routing tree construction.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Fence-aware detailed-routability driven placement.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

2016
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Placement: From Wirelength to Detailed Routability.
IPSJ Trans. Syst. LSI Des. Methodol., 2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Legalization algorithm for multiple-row height standard cell design.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A robust approach for process variation aware mask optimization.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach.
Integr., 2014

Cell density-driven detailed placement with displacement constraint.
Proceedings of the International Symposium on Physical Design, 2014

Triple patterning lithography aware optimization for standard cell based design.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
SRP: simultaneous routing and placement for congestion refinement.
Proceedings of the International Symposium on Physical Design, 2013

Ripple 2.0: high quality routability-driven placement via global router integration.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Fast Power- and Slew-Aware Gated Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A new clock network synthesizer for modern VLSI designs.
Integr., 2012

2010
Clock Network Synthesis with Concurrent Gate Insertion.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

A dual-MST approach for clock network synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010


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