Xiaolong Guo
Orcid: 0000-0001-9896-9407
According to our database1,
Xiaolong Guo
authored at least 47 papers
between 2015 and 2025.
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Bibliography
2025
A Generalize Hardware Debugging Approach for Large Language Models Semi-Synthetic, Datasets.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025
Proceedings of the 26th International Symposium on Quality Electronic Design, 2025
Enhancing LLM Performance on Hardware Design Generation Task via Reinforcement Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2025
Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
2024
PowerScout: Security-Oriented Power Delivery Network Modeling for Side-Channel Vulnerability Analysis.
IEEE Trans. Emerg. Top. Comput., 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Poster: BlindMarket: A Trustworthy Chip Designs Marketplace for IP Vendors and Users.
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024
Poster: Enhance Hardware Domain Specific Large Language Model with Reinforcement Learning for Resilience.
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024
Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
IEEE Trans. Inf. Forensics Secur., 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
2022
FineDIFT: Fine-Grained Dynamic Information Flow Tracking for Data-Flow Integrity Using Coprocessor.
IEEE Trans. Inf. Forensics Secur., 2022
Security Oriented Design Framework for EM Side-Channel Protection in RTL Implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the EMSOFT '21: Proceedings of the 2021 International Conference on Embedded Software, Virtual Event, October 8, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
PowerScout: A Security-Oriented Power Delivery Network Modeling Framework for Cross-Domain Side-Channel Analysis.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020
2019
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2017
Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals.
IEEE Trans. Inf. Forensics Secur., 2017
Eliminating the Hardware-Software Boundary: A Proof-Carrying Approach for Trust Evaluation on Computer Systems.
IEEE Trans. Inf. Forensics Secur., 2017
Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation.
IEEE Trans. Inf. Forensics Secur., 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
2015
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015