Xuan Truong Nguyen

Orcid: 0000-0002-7527-6971

Affiliations:
  • Seoul National University, South Korea


According to our database1, Xuan Truong Nguyen authored at least 40 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2025

FACET: On-the-Fly Activation Compression for Efficient Transformer Training.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2025

OASIS: Outlier-Aware KV Cache Clustering for Scaling LLM Inference in CXL Memory Systems.
IEEE Comput. Archit. Lett., 2025

ENAF: A Multi-Exit Network with an Adaptive Patch Fusion for Large Image Super Resolution.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2025

Mixed INT4-INT8 LLM Quantization via Progressive Layerwise Assignment with Dynamic Sensitivity Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Live Demonstration: A Scalable CNN Accelerator SoC With a Cost-Effective Chip-to-Chip Adapter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Cost-Effective Reconfigurable MCM with Common-Value Elimination and Alignment.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

An Energy-Efficient Daily Surveillance System with DVS-CIS Sensor Fusion and Event-based NPU Triggering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A DVS-CIS Sensor Data Receiver on FPGA with a 10 Gbps MIPI Controller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Live Demonstration: DVS-CIS Sensor Fusion System for Real-Time DNN-Based Object Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Effective Activation Scratchpad Management in NPUs for LLMs via Inter- and Intra-Decoder Allocation.
Proceedings of the IEEE International Conference on Consumer Electronics, 2025

A Winograd-Convolution-Based Accelerator on FPGA for Real-Time Object Detection with Effective On-Chip Buffer Access Patterns.
Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Leveraging Hot Data in a Multi-Tenant Accelerator for Effective Shared Memory Management.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

DEAR-PIM: Processing-in-Memory Architecture with Disaggregated Execution of All-bank Requests.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

Activation Swapping for Feed Forward Networks in Batched LLM Inference on NPU.
Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

2024
A Highly-Scalable Deep-Learning Accelerator With a Cost-Effective Chip-to-Chip Adapter and a C2C-Communication-Aware Scheduler.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

USDN: A Unified Sample-wise Dynamic Network with Mixed-Precision and Early-Exit.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

A Scalable Multi-Chip YOLO Accelerator With a Lightweight Inter-Chip Adapter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Resource-Constrained Spatio-Temporal Super Resolution Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Reconfigurable One-Adder Multiplication for CNN Acceleration.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

Mitigation of Over-Confidence in Scale-Adjusted Training for Early-Exit Networks.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

Real Post-Training Quantization Framework for Resource-Optimized Multiplier in LLMs.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

A Low-Latency and Scalable Vector Engine with Operation Fusion for Transformers.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
Accelerating Super-Resolution Network Inference via Sensitivity-Based Weight Sparsity Allocation.
IEEE Access, 2023

Live Demonstration: Layer-wise Configurable CNN Accelerator with High PE Utilization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

ViT-P3DE∗: Vision Transformer Based Multi-Camera Instance Association with Pseudo 3D Position Embeddings.
Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

Eight-bit Quantization for Super-Resolution Networks and Its Hardware Implementation.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2022
An Energy-Efficient YOLO Accelerator Optimizing Filter Switching Activity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Computation-Skipping Mask Generation for Super-Resolution Networks.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

A Real-time Super-resolution Accelerator Using a big. LITTLE Core Architecture.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Improving Deep-Learning-based Optical Music Recognition for Camera-based Inputs.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2020
An Efficient Sampling Algorithm With a K-NN Expanding Operator for Depth Data Acquisition in a LiDAR System.
IEEE Trans. Circuits Syst. Video Technol., 2020

An MAE-aware ROI Sampling Model for LiDAR.
Proceedings of the International SoC Design Conference, 2020

2019
A Novel FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation and Compensation.
ACM Trans. Reconfigurable Technol. Syst., 2019

ROI-Based LiDAR Sampling Algorithm in on-Road Environment for Autonomous Driving.
IEEE Access, 2019

A Hardware-Friendly Compression Algorithm for Profiling DDR4 Memory Accesses.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2018
A Low-Cost Hardware Design of a 1-D SPIHT Algorithm for Video Display Systems.
IEEE Trans. Consumer Electron., 2018

A New FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation of Operating Condition Variation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


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