Yannick Bonhomme

According to our database1, Yannick Bonhomme authored at least 20 papers between 2001 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Memory Reliability Improvement Based on Maximized Error-Correcting Codes.
J. Electron. Test., 2013

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Memory reliability improvements based on maximized error-correcting codes.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Programmable extended SEC-DED codes for memory errors.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Generalized parity-check matrices for SEC-DED codes with fixed parity.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Error prediction based on concurrent self-test and reduced slack time.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Programmable restricted SEC codes to mask permanent faults in semiconductor memories.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009
Transaction-based modeling for large scale simulations of heterogeneous systems.
Proceedings of the 2nd International Conference on Simulation Tools and Techniques for Communications, 2009

System-level hardware-based protection of memories against soft-errors.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Power-On Controller for high lifetime wireless sensor nodes.
Proceedings of the Wireless Sensor and Actor Networks II, 2008

2006
A Gated Clock Scheme for Low Power Testing of Logic Cores.
J. Electron. Test., 2006

2005
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.
J. Low Power Electron., 2005

2004
Power-Driven Routing-Constrained Scan Chain Design.
J. Electron. Test., 2004

An efficient scan tree design for test time reduction.
Proceedings of the 9th European Test Symposium, 2004

Design of Routing-Constrained Low Power Scan Chains.
Proceedings of the 2004 Design, 2004

2003
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Power Driven Chaining of Flip-Flops in Scan Architectures.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Power: a Big Issue in Large SOC Designs.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
A Gated Clock Scheme for Low Power Scan-Based BIST.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001


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