Valentin Gherman

According to our database, Valentin Gherman authored at least 23 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro.

Bastien Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, Valentin Gherman, M. Pezzin, Florent Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, A. Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas

Proceedings of the IEEE International Memory Workshop, 2023

2020

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits.

Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman

J. Electron. Test., 2020

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities.

Valentin Gherman, Samuel Evain, Bastien Giraud

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2018

Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.

Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Is aproximate computing suitable for selective hardening of arithmetic circuits?

Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics.

Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo

Proceedings of the IEEE International Test Conference, 2017

Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps.

Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman

Proceedings of the 22nd IEEE European Test Symposium, 2017

2014

Error Correction Schemes with Erasure Information for Fast Memories.

Samuel Evain, Valentin Savin, Valentin Gherman

J. Electron. Test., 2014

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.

Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Shadow-scan design with low latency overhead and in-situ slack-time monitoring.

Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

Memory Reliability Improvement Based on Maximized Error-Correcting Codes.

Valentin Gherman, Samuel Evain, Yannick Bonhomme

J. Electron. Test., 2013

Error-correction schemes with erasure information for fast memories.

Samuel Evain, Valentin Gherman

Proceedings of the 18th IEEE European Test Symposium, 2013

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.

Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Memory reliability improvements based on maximized error-correcting codes.

Valentin Gherman, Samuel Evain, Yannick Bonhomme

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Programmable extended SEC-DED codes for memory errors.

Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Generalized parity-check matrices for SEC-DED codes with fixed parity.

Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Error prediction based on concurrent self-test and reduced slack time.

Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Programmable restricted SEC codes to mask permanent faults in semiconductor memories.

Samuel Evain, Yannick Bonhomme, Valentin Gherman

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009

System-level hardware-based protection of memories against soft-errors.

Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme

Proceedings of the Design, Automation and Test in Europe, 2009

2007

Deterministic logic BIST for transition fault testing.

Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers

IET Comput. Digit. Tech., 2007

Synthesis of irregular combinational functions with large don't care sets.

Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2005

Implementing a Scheme for External Deterministic Self-Test.

Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004

Efficient Pattern Mapping for Deterministic Logic BIST.

Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004