Jack Sampson

According to our database1, Jack Sampson authored at least 92 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks.
J. Signal Process. Syst., 2020

Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Adaptive Neural Network Architectures for Power Aware Inference.
IEEE Des. Test, 2020

D-SOAP: Dynamic Spatial Orientation Affinity Prediction for Caching in Multi-Orientation Memory Systems.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

DoubtNet: Using Semantic Context to Enable Adaptive Inference for the IoT.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Integrated CAM-RAM Functionality using Ferroelectric FETs.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Emerging memories as enablers for in-memory layout transformation acceleration and virtualization.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Byzantine-Tolerant Inference in Distributed Deep Intelligent System: Challenges and Opportunities.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs.
IEEE Des. Test, 2019

Context-Aware Collaborative Object Recognition For Distributed Multi Camera Time Series Data.
Proceedings of the Tenth International Symposium on Information and Communication Technology, 2019

Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Context-Aware Convolutional Neural Network over Distributed System in Collaborative Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Symmetric 2-D-Memory Access to Multidimensional Data.
IEEE Trans. Very Large Scale Integr. Syst., 2018

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors.
IEEE Micro, 2018

Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

MDACache: Caching for Multi-Dimensional-Access Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Harnessing Emerging Technology for Compute-in-Memory Support.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Stochastic Functional Verification of DNN Design through Progressive Virtual Dataset Generation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Drones as collaborative sensors for image recognition.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence Systems.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems.
ACM Trans. Embed. Comput. Syst., 2017

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor.
IEEE Trans. Computers, 2017

A Multitask Grocery Assist System for the Visually Impaired: Smart glasses, gloves, and shopping carts provide auditory and tactile feedback.
IEEE Consumer Electron. Mag., 2017

Incidental computing on IoT nonvolatile processors.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Evaluating tradeoffs in granularity and overheads in supporting nonvolatile execution semantics.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Path planning on the TrueNorth neurosynaptic system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Saliency-Driven LCD Power Management System.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Enabling New Computation Paradigms with HyperFET - An Emerging Device.
IEEE Trans. Multi Scale Comput. Syst., 2016

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.
IEEE Micro, 2016

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells.
ACM J. Emerg. Technol. Comput. Syst., 2016

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

LATTE: Low-power Audio Transform with TrueNorth Ecosystem.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Nonvolatile memory design based on ferroelectric FETs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.
ACM Trans. Archit. Code Optim., 2015

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.
IEEE Micro, 2015

Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures.
Proceedings of the 28th International Conference on VLSI Design, 2015

Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Architecture exploration for ambient energy harvesting nonvolatile processors.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Exploring architectural heterogeneity in intelligent vision systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

A scalable architecture for multi-class visual object detection.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Visual co-occurrence network: using context for large-scale object recognition in retail.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Ambient energy harvesting nonvolatile processors: from circuit to system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Core vs. uncore: the heart of darkness.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Cognitive cameras: Assistive vision systems.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
Exploring Energy Scalability in Coprocessor-Dominated Architectures for Dark Silicon.
ACM Trans. Embed. Comput. Syst., 2014

Quality Time: A simple online technique for quantifying multicore execution efficiency.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Exploiting natural redundancy in visual information.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A hardware accelerated multilevel visual classifier for embedded visual-assist systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A task-oriented vision system.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Data driven adaptation for QoS aware embedded vision systems.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

Modeling steep slope devices: From circuits to architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Steep Slope Devices: Enabling New Architectural Paradigms.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
TimeCube: A manycore embedded processor with interference-agnostic progress tracking.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

DR-SNUCA: An energy-scalable dynamically partitioned cache.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Managing distributed UPS energy for effective power capping in data centers.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

GreenDroid: An architecture for the Dark Silicon Age.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future.
IEEE Micro, 2011

QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Efficient complex operators for irregular codes.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Design and architecture of automatically-generated energy- reducing coprocessors.
PhD thesis, 2010

Conservation cores: reducing the energy of mature computations.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2006
Architecture - The potential energy efficiency of vector acceleration.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Detecting phases in parallel applications on shared memory architectures.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Unbounded page-based transactional memory.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
Fast synchronization for chip multiprocessors.
SIGARCH Comput. Archit. News, 2005

The Strong correlation Between Code Signatures and Performance.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005


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