Chi Sung Oh

According to our database1, Chi Sung Oh authored at least 7 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.
IEEE J. Solid State Circuits, 2021

2020

2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017

2016
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2012
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.
IEEE J. Solid State Circuits, 2012

2011
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008
A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array.
IEEE J. Solid State Circuits, 2008


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