Yoonjin Kim
According to our database1,
Yoonjin Kim
authored at least 18 papers
between 2005 and 2023.
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Bibliography
2023
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023
2022
ACM Trans. Comput. Hum. Interact., 2022
Proceedings of the 9th IEEE RAS/EMBS International Conference for Biomedical Robotics and Biomechatronics, 2022
2021
Dynamic optimization of hessian determinant image pyramid for memory-efficient and high performance keypoint detection in SURF.
IET Image Process., 2021
2016
Inter-coarse-grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel-stream on coarse-grained reconfigurable architecture-based multi-core architecture.
IET Circuits Devices Syst., 2016
2014
Ring-based sharing fabric for efficient pipelining of kernel-stream on CGRA-based multi-core architecture.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
Power-Efficient Configuration Cache Structure for Coarse-Grained Reconfigurable Architecture.
J. Circuits Syst. Comput., 2013
2010
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems.
Proceedings of the 46th Design Automation Conference, 2009
2008
Reusable context pipelining for low power coarse-grained reconfigurable architecture.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Dynamically compressible context architecture for low power coarse-grained reconfigurable array.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization.
Proceedings of the 2005 Design, 2005