Youchang Kim

According to our database1, Youchang Kim authored at least 26 papers between 2013 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2018
A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Low-Power Scalable 3-D Face Frontalization Processor for CNN-Based Face Recognition in Mobile Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017
A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

BRAIN: A Low-Power Deep Search Engine for Autonomous Robots.
IEEE Micro, 2017

A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 0.5 V 54 µW Ultra-Low-Power Object Matching Processor for Micro Air Vehicle Navigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses.
IEEE J. Solid State Circuits, 2016

Low-power real-time intelligent SoCs for smart machines.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

14.3 A 0.55V 1.1mW artificial-intelligence processor with PVT compensation for micro robots.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2015
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications.
IEEE J. Solid State Circuits, 2015

A 4.9 mΩ-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System.
IEEE J. Solid State Circuits, 2015

A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor.
IEEE J. Solid State Circuits, 2015

18.3 A 0.5V 54μW ultra-low-power recognition processor with 93.5% accuracy geometric vocabulary tree and 47.5% database compression.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

18.1 A 2.71nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A keypoint-level parallel pipelined object recognition processor with gaze activation image sensor for mobile smart glasses system.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

2014
An Augmented Reality Processor with a Congestion-Aware Network-on-Chip Scheduler.
IEEE Micro, 2014

10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

18.4 A 4.9mΩ-sensitivity mobile electrical impedance tomography IC for early breast-cancer detection system.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 34.1fps scale-space processor with two-dimensional cache for real-time object recognition.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013


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