Yuanhui Ni

According to our database, Yuanhui Ni authored at least 8 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment.

Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang

Sustain. Comput. Informatics Syst., 2019

2018

面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM).

Yuanhui Ni, Weiwen Chen, Lei Wang, Keni Qiu

计算机科学, 2018

Low power driven loop tiling for RRAM crossbar-based CNN.

Yuanhui Ni, Keni Qiu, Weiwen Chen, Lixue Xia, Yu Wang

Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN.

Yuanhui Ni, Weiwen Chen, Wenjuan Cui, Yuanchun Zhou, Keni Qiu

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers.

Yuanhui Ni, Zhiyao Gong, Weiwen Chen, Chengmo Yang, Keni Qiu

VLSI Design, 2017

Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment.

Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang

Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus.

Weiwen Chen, Keni Qiu, Jiqin Zhou, Yuanhui Ni, Yuanchao Xu

Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

2016

An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor.

Keni Qiu, Yuanhui Ni, Weigong Zhang, Jing Wang, Xiaoqiang Wu, Chun Jason Xue, Tao Li

Proceedings of the 34th IEEE International Conference on Computer Design, 2016