Keni Qiu

Orcid: 0000-0002-5851-777X

According to our database1, Keni Qiu authored at least 59 papers between 2013 and 2023.

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Bibliography

2023
Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies.
ACM Trans. Embed. Comput. Syst., March, 2023

A<sup>2</sup>OP: an A* Algorithm OPtimizer with the Heuristic Function for PCB Automatic Routing.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

EagerReuse: An Efficient Memory Reuse Approach for Complex Computational Graph.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

ResCheck: Resilient Checkpointing for Energy Harvesting Systems.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022
Publisher Correction: Smart scheduler: an adaptive NVM-aware thread scheduling approach on NUMA systems.
CCF Trans. High Perform. Comput., December, 2022

Smart scheduler: an adaptive NVM-aware thread scheduling approach on NUMA systems.
CCF Trans. High Perform. Comput., December, 2022

REC: REtime convolutional layers in energy harvesting ReRAM-based CNN accelerators.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021
MaxTracker: Continuously Tracking the Maximum Computation Progress for Energy Harvesting ReRAM-based CNN Accelerators.
ACM Trans. Embed. Comput. Syst., 2021

2020
ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Insights and Optimizations on IR-drop Induced Sneak-Path for RRAM Crossbar-based Convolutions.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment.
Sustain. Comput. Informatics Syst., 2019

Queuing theory guided performance evaluation and energy optimization for a reconfigurable high speed device interconnected bus.
Sustain. Comput. Informatics Syst., 2019

BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors.
Microelectron. J., 2019

Mixed Precision Quantization Scheme for Re-configurable ReRAM Crossbars Targeting Different Energy Harvesting Scenarios.
Proceedings of the Internet of Things. A Confluence of Many Disciplines, 2019

PAPS: power budget-aware pipeline scheduling for an embedded ReRAM-based accelerator.
Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 2019

Leveraging Energy Cycle Regularity to Predict Adaptive Mode for Non-volatile Processors.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM).
计算机科学, 2018

Efficient energy management by exploiting retention state for self-powered nonvolatile processors.
J. Syst. Archit., 2018

Low power driven loop tiling for RRAM crossbar-based CNN.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

Exporting Transactional Interface to Applications in Log-Structured File Systems.
Proceedings of the 2018 IEEE International Conference on Networking, 2018

A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Dual-threshold directed execution progress maximization for nonvolatile processors.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers.
VLSI Design, 2017

On the Implication of NTC versus Dark Silicon on Emerging Scale-Out Workloads: The Multi-Core Architecture Perspective.
IEEE Trans. Parallel Distributed Syst., 2017

基于排队论的UM-BUS总线性能建模与评估 (Queuing Theory-guided Performance Evaluation on Reconfigurable High-speed Device Connected Bus).
计算机科学, 2017

Data re-allocation enabled cache locking for embedded systems.
J. Syst. Archit., 2017

Expected Completion Time Aware Message Scheduling for UM-BUS Interconnected System.
IEEE Access, 2017

Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

Retention state-enabled and progress-driven energy management for self-powered nonvolatile processors.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

Energy-Efficient Cache Management for NVM-Based IoT Systems.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Retention state-aware energy management for efficient nonvolatile processors: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

'The danger of sleeping', an exploration of security in non-volatile processors.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
A Novel Time Synchronization Method for Dynamic Reconfigurable Bus.
VLSI Design, 2016

FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW.
VLSI Design, 2016

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems.
IEEE Trans. Computers, 2016

Reducing Synchronization Cost for Single-Level Store in Mobile Systems.
J. Comput. Sci. Technol., 2016

Redesigning software and systems for non-volatile processors on self-powered devices.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

UM-BUS: An online fault-tolerant bus for embedded systems.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Exploring Variation-Aware Fault-Tolerant Cache under Near-Threshold Computing.
Proceedings of the 45th International Conference on Parallel Processing, 2016

An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Refresh-aware loop scheduling for high performance low power volatile STT-RAM.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Mitigating sync overhead in single-level store systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Near threshold cloud processors for dark silicon mitigation: the impact on emerging scale-out workloads.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Heterogeneous energy-efficient cache design in warehouse scale computers.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2014

Error Model Guided Joint Performance and Endurance Optimization for Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Data re-allocation enabled cache locking for embedded systems.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013


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