Yuanchao Xu

Affiliations:
  • Capital Normal University, Beijing, China


According to our database1, Yuanchao Xu authored at least 27 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
EagerReuse: An Efficient Memory Reuse Approach for Complex Computational Graph.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

An Empirical Study of Memory Pool Based Allocation and Reuse in CUDA Graph.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

iNUMAlloc: Towards Intelligent Memory Allocation for AI Accelerators with NUMA.
Proceedings of the IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2023

2022
Towards Efficient Elastic Parallelism for Deep Learning Processor.
Proceedings of the IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2022

2021
Global-view based Task Migration for Deep Learning Processor.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

2020
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment.
Sustain. Comput. Informatics Syst., 2019

BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors.
Microelectron. J., 2019

Asymmetry & Locality-Aware Cache Bypass and Flush for NVM-Based Unified Persistent Memory.
Proceedings of the 2019 IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2019

Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
NMST: 一种基于线段树的持久性内存管理优化方法 (NMST: A Persistent Memory Management Optimization Approach Based on Segment Tree).
计算机科学, 2018

Efficient energy management by exploiting retention state for self-powered nonvolatile processors.
J. Syst. Archit., 2018

A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Data re-allocation enabled cache locking for embedded systems.
J. Syst. Archit., 2017

Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

Retention state-enabled and progress-driven energy management for self-powered nonvolatile processors.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

Energy-Efficient Cache Management for NVM-Based IoT Systems.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

i-BEP: A non-redundant and high-concurrency memory persistency model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Reducing Synchronization Cost for Single-Level Store in Mobile Systems.
J. Comput. Sci. Technol., 2016

NVM-Assisted Non-redundant Logging for Android Systems.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

Empirical study of redo and undo logging in persistent memory.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Refresh-aware loop scheduling for high performance low power volatile STT-RAM.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Mitigating sync overhead in single-level store systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Rethinking manycore caches for scale-out applications.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015


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