Yuanlong Xiao

According to our database, Yuanlong Xiao authored at least 15 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.

Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Asymmetry in Butterfly Fat Tree FPGA NoC.

Dongjoon Park, Zhijing Yao, Yuanlong Xiao, André DeHon

Proceedings of the International Conference on Field Programmable Technology, 2023

2022

Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration.

Dongjoon Park, Yuanlong Xiao, André DeHon

Proceedings of the International Conference on Field-Programmable Technology, 2022

HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation.

Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers.

Yuanlong Xiao, André DeHon

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development.

Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021

Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation.

André DeHon, Hans Giesen, Nik Sultana, Yuanlong Xiao

CoRR, 2021

HLS-Compatible, Embedded-Processor Stream Links.

Eric Micallef, Yuanlong Xiao, André DeHon

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

Fast Linking of Separately-Compiled FPGA Blocks without a NoC.

Yuanlong Xiao, Syed Tousif Ahmed, André DeHon

Proceedings of the International Conference on Field-Programmable Technology, 2020

2019

Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks.

Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon

Proceedings of the International Conference on Field-Programmable Technology, 2019

An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization.

Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits.

Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Case for Fast FPGA Compilation Using Partial Reconfiguration.

Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2016

A universal automatic on-chip measurement of FPGA's internal setup and hold times.

Yuanlong Xiao, Jian Wang, Jinmei Lai

IEICE Electron. Express, 2016

2015

A power efficient current-mode differential driver for FPGAs.

Yuanlong Xiao, Jian Wang, Jinmei Lai

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015