Chris Lavin

Orcid: 0000-0002-8091-0973

Affiliations:
  • Xilinx Research Labs, Longmont, CO, USA
  • Xilinx, San Jose, CA, USA
  • Brigham Young University, Provo, UT, USA


According to our database1, Chris Lavin authored at least 17 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Open-source and FPGAs: Hardware, Software, Both or None?
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2022

RapidStream: Parallel Physical Implementation of FPGA HLS Designs.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2021
Software-like Compilation for Data Center FPGA Accelerators.
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

2019
An Open-Source Lightweight Timing Model for RapidWright.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Build Your Own Domain-specific Solutions with RapidWright: Invited Tutorial.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
RapidWright: Enabling Custom Crafted Implementations for FPGAs.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Space-Time Coding for Aeronautical Telemetry: Part I - Estimators.
IEEE Trans. Aerosp. Electron. Syst., 2017

Space-Time Coding for Aeronautical Telemetry: Part II - Decoder and System Performance.
IEEE Trans. Aerosp. Electron. Syst., 2017

2013
Improving clock-rate of hard-macro designs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Impact of hard macro size on FPGA clock rate and place/route time.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2011
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Rapid prototyping tools for FPGA designs: RapidSmith.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Using Hard Macros to Reduce FPGA Compilation Time.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010


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