Yulei Zhang

Affiliations:
  • University of California San Diego, Department of Electrical and Computer Engineering, La Jolla, CA, USA


According to our database1, Yulei Zhang authored at least 11 papers between 2008 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2014
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2011
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Prediction and Comparison of High-Performance On-Chip Global Interconnection.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

2009
Prediction of high-performance on-chip global interconnection.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

On the bound of time-domain power supply noise based on frequency-domain target impedance.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Design methodology of high performance on-chip global interconnect using terminated transmission-line.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

High performance on-chip differential signaling using passive compensation for global communication.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
On-chip high performance signaling using passive compensation.
Proceedings of the 26th International Conference on Computer Design, 2008

Low Power Passive Equalizer Design for Computer Memory Links.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008


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