Renshen Wang

According to our database1, Renshen Wang authored at least 13 papers between 2005 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip.
Proceedings of the International Symposium on Physical Design, 2012

2011
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.
ACM Trans. Design Autom. Electr. Syst., 2010

Physical synthesis of bus matrix for high bandwidth low power on-chip communications.
Proceedings of the 2010 International Symposium on Physical Design, 2010

2009
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
Proceedings of the 27th International Conference on Computer Design, 2009

On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Octilinear redistributive routing in bump arrays.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
Proceedings of the 46th Design Automation Conference, 2009

Noise minimization during power-up stage for a multi-domain power network.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
3-D floorplanning using labeled tree and dual sequences.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Low Power Passive Equalizer Design for Computer Memory Links.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

2006
Layer minimization of escape routing in area array packaging.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
An improved P-admissible floorplan representation based on Corner Block List.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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