Yusuke Iguchi

According to our database1, Yusuke Iguchi authored at least 10 papers between 2007 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2011
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.
IPSJ Trans. Syst. LSI Des. Methodol., 2011

2010
Fixed Point Data Type Modeling for High Level Synthesis.
IEICE Trans. Electron., 2010

2009
A Dependable SRAM with 7T/14T Memory Cells.
IEICE Trans. Electron., 2009

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.
IEICE Trans. Electron., 2008

Quality of a Bit (QoB): A New Concept in Dependable SRAM.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Area Optimization in 6T and 8T SRAM Cells Considering <i>V</i><sub>th</sub> Variation in Future Processes.
IEICE Trans. Electron., 2007

Area Comparison between 6T and 8T SRAM Cells in Dual-<i>V</i><sub>dd</sub> Scheme and DVS Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007


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