Shunsuke Okumura

According to our database, Shunsuke Okumura authored at least 36 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications.

Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2019

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm².

Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2014

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.

Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2014

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.

Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout.

Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM.

Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2013

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique.

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme.

Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

IPSJ Trans. Syst. LSI Des. Methodol., 2012

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme.

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2012

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process.

Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.

Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2012

A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells.

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme.

Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi

IEICE Trans. Electron., 2012

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique.

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Electron. Express, 2012

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy.

Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Electron. Express, 2012

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.

Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Bit error rate estimation in SRAM considering temperature fluctuation.

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.

Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores.

Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011

Session Initiation Protocol (SIP) Usage of the Offer/Answer Model.

Shunsuke Okumura, Takuya Sawada, Paul H. Kyzivat

RFC, August, 2011

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.

Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

IPSJ Trans. Syst. LSI Des. Methodol., 2011

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory.

Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control.

Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM.

Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V.

Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10^-19.

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 37th European Solid-State Circuits Conference, 2011

Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units.

Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy.

Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.

Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

7T SRAM enabling low-energy simultaneous block copy.

Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Dependable SRAM with 7T/14T Memory Cells.

Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2009

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.

Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.

Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.

Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2008

Quality of a Bit (QoB): A New Concept in Dependable SRAM.

Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008