Hiroki Noguchi
According to our database1,
Hiroki Noguchi
authored at least 38 papers
between 2006 and 2024.
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Bibliography
2024
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10<sup>12</sup> Write Endurance and Integrated Margin-Expansion Schemes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
RoboCup2022 KidSize League Winner CIT Brains: Open Platform Hardware SUSTAINA-OP and Software.
Proceedings of the RoboCup 2022:, 2022
2020
Network theory-based accident scenario analysis for hazardous material transport: A case study of liquefied petroleum gas transport in japan.
Reliab. Eng. Syst. Saf., 2020
2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
2014
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.
Proceedings of the Symposium on VLSI Circuits, 2014
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
2011
J. Inf. Process., 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition.
IEICE Trans. Electron., 2011
A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition.
IEICE Trans. Electron., 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system.
Proceedings of the 10th Annual Conference of the International Speech Communication Association, 2009
2008
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEICE Trans. Electron., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
2007
Area Optimization in 6T and 8T SRAM Cells Considering <i>V</i><sub>th</sub> Variation in Future Processes.
IEICE Trans. Electron., 2007
Area Comparison between 6T and 8T SRAM Cells in Dual-<i>V</i><sub>dd</sub> Scheme and DVS Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
2006
A 0.3-V Operating, <i>V</i><sub>th</sub>-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006