Hiroki Noguchi

According to our database¹, Hiroki Noguchi authored at least 38 papers between 2006 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2024

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.

[BibT_eX]

[DOI]

Tsung-Yung Jonathan Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

RoboCup2022 KidSize League Winner CIT Brains: Open Platform Hardware SUSTAINA-OP and Software.

[BibT_eX]

[DOI]

Proceedings of the RoboCup 2022:, 2022

2020

Network theory-based accident scenario analysis for hazardous material transport: A case study of liquefied petroleum gas transport in japan.

[BibT_eX]

[DOI]

Hiroki Noguchi

Shunichi Hienuki

Masaaki Fuse

Reliab. Eng. Syst. Saf., 2020

2017

Novel memory hierarchy with e-STT-MRAM for near-future applications.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

Data-Intensive Sound Acquisition System with Large-scale Microphone Array.

[BibT_eX]

[DOI]

J. Inf. Process., 2011

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2011

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2011

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2011

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network.

[BibT_eX]

[DOI]

Proceedings of 20th International Conference on Computer Communications and Networks, 2011

A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Parallel-processing VLSI architecture for mixed integer linear programming.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Intelligent ubiquitous sensor network for sound acquisition.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Live demonstration: Intelligent ubiquitous sensor network for sound acquisition.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A 34.7-mW quad-core MIQP solver processor for robot control.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Dependable SRAM with 7T/14T Memory Cells.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system.

[BibT_eX]

[DOI]

Proceedings of the INTERSPEECH 2009, 2009

2008

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2008

Quality of a Bit (QoB): A New Concept in Dependable SRAM.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2007

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Hiroki Noguchi

Timeline

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On csauthors.net:

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