Yutaka Ide

According to our database1, Yutaka Ide authored at least 2 papers between 2015 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015


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