Noriaki Shirai

According to our database1, Noriaki Shirai authored at least 9 papers between 2006 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Real-time stereo vision system at nighttime with noise reduction using simplified non-local matching cost.
Proceedings of the 2016 IEEE Intelligent Vehicles Symposium, 2016

2015
Accurate 3D Reconstruction from Naturally Swaying Cameras.
Proceedings of the VISAPP 2015, 2015

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE.
IEEE J. Solid State Circuits, 2014

A real-time dense stereo matching method for critical environment sensing in autonomous driving.
Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

2006
An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tuners.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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