Hideki Kano

According to our database, Hideki Kano authored at least 8 papers between 1998 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.

Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS.

Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Tomoyuki Arai, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE.

Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori

IEEE J. Solid State Circuits, 2014

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE.

Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets.

Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2002

A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology.

Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe

IEEE J. Solid State Circuits, 2002

1998

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line.

Satoshi Eto, Masato Matsumiya, Masato Takita, Yuki Ishii, Toshikazu Nakamura, Kuninori Kawabata, Hideki Kano, Ayako Kitamoto, Toshimi Ikeda, Toru Koga, Mitsuhiro Higashiho, Yuji Serizawa, Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Masao Taguchi

IEEE J. Solid State Circuits, 1998