Takayuki Shibasaki

According to our database1, Takayuki Shibasaki authored at least 23 papers between 2007 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 30Gb/s 2x Half-Baud-Rate CDR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
F5: Advanced optical communication: From devices, circuits, and architectures to algorithms.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.
IEEE J. Solid State Circuits, 2017

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Session 6 overview: Ultra-high-speed wireline.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.
IEEE J. Solid State Circuits, 2013

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order <i>LC</i> Oscillator Topology for Wide Locking Range.
IEICE Trans. Electron., 2011

2010
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.
IEEE J. Solid State Circuits, 2008

2007
18-GHz Clock Distribution Using a Coupled VCO Array.
IEICE Trans. Electron., 2007


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