Thomas F. Wenisch

Orcid: 0000-0001-9560-2124

Affiliations:
  • University of Michigan


According to our database1, Thomas F. Wenisch authored at least 123 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
FinePack: Transparently Improving the Efficiency of Fine-Grained Transfers in Multi-GPU Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
Finding and Indexing Vehicle Maneuvers From Dashboard Camera Video.
IEEE Trans. Intell. Transp. Syst., 2022

2021
Front-End Architecture Design for Low-Complexity 3-D Ultrasound Imaging Based on Synthetic Aperture Sequential Beamforming.
IEEE Trans. Very Large Scale Integr. Syst., 2021

CliqueMap: productionizing an RMA-based distributed caching system.
Proceedings of the ACM SIGCOMM 2021 Conference, Virtual Event, USA, August 23-27, 2021., 2021

GPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Jigsaw: A Slice-and-Dice Approach to Non-uniform FFT Acceleration for MRI Image Reconstruction.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

μSteal: a theory-backed framework for preemptive work and resource stealing in mixed-criticality microservices.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

HyperData: A Data Transfer Accelerator for Software Data Planes Based on Targeted Prefetching.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Parslo: A Gradient Descent-based Approach for Near-optimal Partial SLO Allotment in Microservices.
Proceedings of the SoCC '21: ACM Symposium on Cloud Computing, 2021

2020
Tetris: Using Software/Hardware Co-Design to Enable Handheld, Physics-Limited 3D Plane-Wave Ultrasound Imaging.
IEEE Trans. Computers, 2020

1RMA: Re-envisioning Remote Memory Access for Multi-tenant Datacenters.
Proceedings of the SIGCOMM '20: Proceedings of the 2020 Annual conference of the ACM Special Interest Group on Data Communication on the applications, 2020

HyperPlane: A Scalable Low-Latency Notification Accelerator for Software Data Planes.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Relaxed Persist Ordering Using Strand Persistency.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Q-Zilla: A Scheduling Framework and Core Microarchitecture for Tail-Tolerant Microservices.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Cross-Failure Bug Detection in Persistent Memory Programs.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
The Queuing-First Approach for Tail Management of Interactive Services.
IEEE Micro, 2019

Language Support for Memory Persistency.
IEEE Micro, 2019

Breaking Virtual Memory Protection and the SGX Ecosystem with Foreshadow.
IEEE Micro, 2019

How economic theories can help computers beat the heat: technical perspective.
Commun. ACM, 2019

NDA: Preventing Speculative Execution Attacks at Their Source.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Classifying Ego-Vehicle Road Maneuvers from Dashcam Video.
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019

SoftSKU: optimizing server architectures for microservice diversity @scale.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Physical Representation-Based Predicate Optimization for a Visual Analytics Database.
Proceedings of the 35th IEEE International Conference on Data Engineering, 2019

Express-Lane Scheduling and Multithreading to Minimize the Tail Latency of Microservices.
Proceedings of the 2019 IEEE International Conference on Autonomic Computing, 2019

Enhancing Server Efficiency in the Face of Killer Microseconds.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Software Wear Management for Persistent Memories.
Proceedings of the 17th USENIX Conference on File and Storage Technologies, 2019

Tetris: A Streaming Accelerator for Physics-Limited 3D Plane-Wave Ultrasound Imaging.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Software Data Planes: You Can't Always Spin to Win.
Proceedings of the ACM Symposium on Cloud Computing, SoCC 2019, 2019

2018
Top Picks from the 2017 Computer Architecture Conferences.
IEEE Micro, 2018

Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design.
IEEE Des. Test, 2018

Rethinking Numerical Representations for Deep Neural Networks.
CoRR, 2018

Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution.
Proceedings of the 27th USENIX Security Symposium, 2018

Persistency for synchronization-free regions.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

µTune: Auto-Tuned Threading for OLDI Microservices.
Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation, 2018

μ Suite: A Benchmark Suite for Microservices.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

2017
Reining in Long Tails in Warehouse-Scale Computers with Quick Voltage Boosting Using Adrenaline.
ACM Trans. Comput. Syst., 2017

Energy-Efficient Data Centers.
IEEE Internet Comput., 2017

Deconstructing the Tail at Scale Effect Across Network Protocols.
CoRR, 2017

Democratizing Design for Future Computing Platforms.
CoRR, 2017

A Top-Down Approach to Achieving Performance Predictability in Database Systems.
Proceedings of the 2017 ACM International Conference on Management of Data, 2017

BiNoCHS: Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Message from the program co-chairs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Language-level persistency.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Statistical Analysis of Latency Through Semantic Profiling.
Proceedings of the Twelfth European Conference on Computer Systems, 2017

Thermostat: Application-transparent Page Management for Two-tiered Main Memory.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHS.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Exploring Fine-Grained Heterogeneity with Composite Cores.
IEEE Trans. Computers, 2016

Identifying the Major Sources of Variance in Transaction Latencies: Towards More Predictable Databases.
CoRR, 2016

21st Century Computer Architecture.
CoRR, 2016

Arch2030: A Vision of Computer Architecture Research over the Next 15 Years.
CoRR, 2016

Low Complexity 3D Ultrasound Imaging Using Synthetic Aperture Sequential Beamforming.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Delegated persist ordering.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

HARE: Hardware accelerator for regular expressions.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

HAWK: Hardware support for unstructured log processing.
Proceedings of the 32nd IEEE International Conference on Data Engineering, 2016

Selective GPU caches to eliminate CPU-GPU HW cache coherence.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

High-Performance Transactions for Persistent Memories.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015
High Frame Rate 3-D Ultrasound Imaging Using Separable Beamforming.
J. Signal Process. Syst., 2015

Separable Beamforming For 3-D Medical Ultrasound Imaging.
IEEE Trans. Signal Process., 2015

Memory Persistency: Semantics for Byte-Addressable Nonvolatile Memory Technologies.
IEEE Micro, 2015

Low cost clutter filter for 3D ultrasonic flow estimation.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Unlocking bandwidth for GPUs in CC-NUMA systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
A Primer on Hardware Prefetching
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01743-8, 2014

Sonic Millip3De: An Architecture for Handheld 3D Ultrasound.
IEEE Micro, 2014

A low complexity scheme for accurate 3D velocity estimation in ultrasound systems.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

The Mystery Machine: End-to-end Performance Analysis of Large-scale Internet Services.
Proceedings of the 11th USENIX Symposium on Operating Systems Design and Implementation, 2014

Simulating DRAM controllers for future system architecture exploration.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Memory persistency.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Heterogeneous microarchitectures trump voltage scaling for low-power cores.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Storage Management in the NVRAM Era.
Proc. VLDB Endow., 2013

Designing for Responsiveness with Computational Sprinting.
IEEE Micro, 2013

Utilizing Dark Silicon to Save Energy with Computational Sprinting.
IEEE Micro, 2013

Separable beamforming for 3-D synthetic aperture ultrasound imaging.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

RDIP: return-address-stack directed instruction prefetching.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Hardware acceleration for similarity measurement in natural language processing.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Thin servers with smart pipes: designing SoC accelerators for memcached.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Minimizing Remote Accesses in MapReduce Clusters.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Computational sprinting on a hardware/software testbed.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012
Energy-Aware Computing.
IEEE Micro, 2012

Active Low-Power Modes for Main Memory with MemScale.
IEEE Micro, 2012

Swizzle-Switch Networks for Many-Core Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Composite Cores: Pushing Heterogeneity Into a Core.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

CoScale: Coordinating CPU and Memory System DVFS in Server Systems.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

BigHouse: A simulation infrastructure for data center systems.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

MultiScale: memory system DVFS with multiple memory controllers.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Embedded way prediction for last-level caches.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Computational sprinting.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

System-level implications of disaggregated memory.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems.
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

DreamWeaver: architectural support for deep sleep.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011
The PowerNap Server Architecture.
ACM Trans. Comput. Syst., 2011

Spatial Memory Streaming.
J. Instr. Level Parallelism, 2011

Do Query Optimizers Need to be SSD-aware?
Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2011

Towards a scalable data center-level evaluation methodology.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Does low-power design imply energy efficiency for data centers?
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Power management of online data-intensive services.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Full-system analysis and characterization of interactive smartphone applications.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

MemScale: active low-power modes for main memory.
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

2010
Making Address-Correlated Prefetching Practical.
IEEE Micro, 2010

Peak power modeling for data center servers with switched-mode power supplies.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Power routing: dynamic power provisioning in the data center.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
Thinking outside the box: power management at the system level & beyond.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Spatio-temporal memory streaming.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Disaggregated memory for expansion and sharing in blade servers.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

InvisiFence: performance-transparent memory ordering in conventional multiprocessors.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Practical off-chip meta-data for temporal memory streaming.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

PowerNap: eliminating server idle power.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008
Temporal instruction fetch streaming.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Temporal streams in commercial server applications.
Proceedings of the 4th International Symposium on Workload Characterization (IISWC 2008), 2008

2007
Mechanisms for store-wait-free multiprocessors.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Statistical sampling of microarchitecture simulation.
ACM Trans. Model. Comput. Simul., 2006

SimFlex: Statistical Sampling of Computer System Simulation.
IEEE Micro, 2006

Simulation sampling with live-points.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Spatial Memory Streaming.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005
TurboSMARTS: accurate microarchitecture simulation sampling in minutes.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2005

Temporal Streaming of Shared Memory.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Store-Ordered Streaming of Shared Memory.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture.
SIGMETRICS Perform. Evaluation Rev., 2004

Memory coherence activity prediction in commercial workloads.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

2003
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003


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