Cristiana Bolchini

According to our database1, Cristiana Bolchini authored at least 133 papers between 1993 and 2020.

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Bibliography

2020
A Neural Network Based Fault Management Scheme for Reliable Image Processing.
IEEE Trans. Computers, 2020

Holding Conferences Online due to COVID-19: The DATE Experience.
IEEE Des. Test, 2020

Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Lightweight Fault Detection and Management for Image Restoration.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Scalable analytical model for reliability measures in aging VLSI by interacting Markovian agents.
Perform. Evaluation, 2019

HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A Smart Fault Detection Scheme for Reliable Image Processing Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A runtime controller for openCL applications on heterogeneous system architectures.
SIGBED Rev., 2018

Approximation-aware coordinated power/performance management for heterogeneous multi-cores.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Can Dark Silicon Be Exploited to Prolong System Lifetime?
IEEE Des. Test, 2017

A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis.
IEEE Des. Test, 2017

Scalable analytical model of the reliability of multi-core systems-on-chip by interacting Markovian agents.
Proceedings of the 11th EAI International Conference on Performance Evaluation Methodologies and Tools, 2017

A dynamic reliability management framework for heterogeneous multicore systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
IEEE Trans. Computers, 2016

A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards.
IEEE Trans. Computers, 2016

Runtime resource management for lifetime extension in multi-core systems.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Using just-in-time code generation for transparent resource management in heterogeneous systems.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

Combined on-line lifetime-energy optimization for asymmetric multicores.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Workload-aware power optimization strategy for asymmetric multiprocessors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Dependable Multicore Architectures at Nanoscale: The View From Europe.
IEEE Des. Test, 2015

An orchestrated approach to efficiently manage resources in heterogeneous system architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

A configurable board-level adaptive incremental diagnosis technique based on decision trees.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Design of Hardened Embedded Systems on Multi-FPGA Platforms.
ACM Trans. Design Autom. Electr. Syst., 2014

Editorial.
Microprocess. Microsystems, 2014

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

A lightweight and open-source framework for the lifetime estimation of multicore systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Design and implementation of a self-healing processor on SRAM-based FPGAs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Machine learning-based techniques for incremental functional diagnosis: A comparative analysis.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Reliability-Driven System-Level Synthesis for Mixed-Critical Embedded Systems.
IEEE Trans. Computers, 2013

CARVE: Context-aware automatic view definition over relational databases.
Inf. Syst., 2013

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms.
J. Electron. Test., 2013

Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems.
J. Electron. Test., 2013

A data mining approach to incremental adaptive functional diagnosis.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Run-time mapping for reliable many-cores based on energy/performance trade-offs.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Analysis and comparison of functional verification and ATPG for testing design reliability.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

A framework to model self-adaptive Computing Systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
Context Support for Designing Analytical Queries.
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012

Context-Aware Knowledge Querying in a Networked Enterprise.
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012

Increasing autonomous fault-tolerant FPGA-based systems' lifetime.
Proceedings of the 17th IEEE European Test Symposium, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

An adaptive approach for online fault management in many-core architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs.
IEEE Trans. Computers, 2011

The ESTEEM platform: enabling P2P semantic collaboration through emerging collective knowledge.
J. Intell. Inf. Syst., 2011

Context Modeling and Context Awareness: steps forward in the Context-ADDICT project.
IEEE Data Eng. Bull., 2011

A reliable fault classifier for dependable systems on SRAM-based FPGAs.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Combined architecture and hardening techniques exploration for reliable embedded system design.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Reliability-Aware Partitioner for Multi-FPGA Platforms.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

An Application-Level Dependability Analysis Framework for Embedded Systems.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Optimal Test Set Selection for Fault Diagnosis Improvement.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Emergent Semantics and Cooperation in Multi-knowledge Communities: the ESTEEM Approach.
World Wide Web, 2010

Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures.
IEEE Trans. Computers, 2010

Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation.
IEEE Embed. Syst. Lett., 2010

Improving fault diagnosis accuracy by automatic test set modification.
Proceedings of the 2011 IEEE International Test Conference, 2010

An integrated flow for the design of hardened circuits on SRAM-based FPGAs.
Proceedings of the 15th European Test Symposium, 2010

A Formal Condition to Stop an Incremental Automatic Functional Diagnosis.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Reliability-Driven System-Level Synthesis of Embedded Systems.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Test Selection Policies for Faster Incremental Fault Detection.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A multi-objective genetic algorithm framework for design space exploration of reliable FPGA-based systems.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010

2009
Context information for knowledge reshaping.
Int. J. Web Eng. Technol., 2009

Guest Editorial.
J. Electron. Test., 2009

And what can context do for data?
Commun. ACM, 2009

Multi-level fault modeling for transaction-level specifications.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

An Incremental Approach to Functional Diagnosis.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Software and Hardware Techniques for SEU Detection in IP Processors.
J. Electron. Test., 2008

Fault Models and Injection Strategies in SystemC Specifications.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Design Space Exploration for the Design of Reliable.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Data and web management research at Politecnico di Milano.
SIGMOD Rec., 2007

A data-oriented survey of context models.
SIGMOD Rec., 2007

A methodology for a Very Small Data Base design.
Inf. Syst., 2007

CADD: A Tool for Context Modeling and Data Tailoring.
Proceedings of the 8th International Conference on Mobile Data Management (MDM 2007), 2007

SEU mitigation for sram-based fpgas through dynamic partial reconfiguration.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Relational Data Tailoring Through View Composition.
Proceedings of the Conceptual Modeling, 2007

TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Using Context for the Extraction of Relational Views.
Proceedings of the Modeling and Using Context, 2007

2006
Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs.
J. Syst. Archit., 2006

Context-Driven Data Filtering: A Methodology.
Proceedings of the On the Move to Meaningful Internet Systems 2006: OTM 2006 Workshops, 2006

Context Integration for Mobile Data Tailoring.
Proceedings of the 7th International Conference on Mobile Data Management (MDM 2006), 2006

Combined software and hardware techniques for the design of reliable IP processors.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
A model of soft error effects in generic IP processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Reliable System Specification for Self-Checking Data-Paths.
Proceedings of the 2005 Design, 2005

Toward an FPGA implementation of XCS.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005

2004
A context-aware methodology for very small data base design.
SIGMOD Rec., 2004

Guest editorial.
J. Syst. Archit., 2004

PoLiDBMS: Design and Prototype Implementation of a DBMS for Portable Devices.
Proceedings of the Twelfth Italian Symposium on Advanced Database Systems, 2004

Reliable System Co-Design: The FIR Case Study.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
A software methodology for detecting hardware faults in VLIW data paths.
IEEE Trans. Reliab., 2003

Logical and physical design issues for smart card databases.
ACM Trans. Inf. Syst., 2003

The design of reliable devices for mission-critical applications.
IEEE Trans. Instrum. Meas., 2003

An Integrated Design Approach for Self-Checking FPGAs.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Reliability Properties Assessment at System Level: A Co-Design Framework.
J. Electron. Test., 2002

Smart card embedded information systems: a methodology for privacy oriented architectural design.
Data Knowl. Eng., 2002

Physical and Logical Data Structures for Very Small Databases.
Proceedings of the Decimo Convegno Nazionale su Sistemi Evoluti per Basi di Dati, 2002

A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Designing Self-Checking FPGAs through Error Detection Codes.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
On-line fault detection in a hardware/software co-design environment.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Designing Reliable Embedded Systems Based on 32 Bit Microprocessors.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A Software Methodology for Detecting Hardware Faults in VLIW Data Paths.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.
IEEE Trans. Very Large Scale Integr. Syst., 2000

1999
A Synthesis Methodology Aimed at Improving the Quality of TSC Devices.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
Fault Analysis for Networks with Concurrent Error Detection.
IEEE Des. Test Comput., 1998

Concurrent Error Detection at Architectural Level.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Fault Analysis in Networks with Concurrent Error Detection Properties.
Proceedings of the 1998 Design, 1998

1997
Software methodologies in VHDL code analysis.
J. Syst. Archit., 1997

A TSC Evaluation Function for Combinational Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Designing Networks with Error Detection Properties through the Fault-Error Relation.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

A novel methodology for designing TSC networks based on the parity bit code.
Proceedings of the European Design and Test Conference, 1997

1996
Software methodologies for VHDL code static analysis based on flow graphs.
Proceedings of the conference on European design automation, 1996

Redundant Faults in TSC Networks: Definition and Removal.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Fault detection and fault tolerance issues at CMOS level through AUED encoding.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
A new switching-level approach to multiple-output functions synthesis.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

An Output/State Encoding for Self-Checking Finite State Machine.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A BDD Based Algorithm for Detecting Difficult Faults.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Self-checking FSMs based on a constant distance state encoding.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
Two-Dimensional Sequential Array Architectures: Design for Testability Approaches.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

CMOS Reliability Improvements Through a New Fault Tolerant Technique.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A CMOS Fault Tolerant Architecture for Swith-Level Faults.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
FSM fault models impact on test performances.
Microprocess. Microprogramming, 1993

A design methodology for the correct specification of VLSI systems.
Microprocess. Microprogramming, 1993


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