Zeyi Wang
Orcid: 0000-0002-2786-6969
According to our database1,
Zeyi Wang
authored at least 29 papers
between 1992 and 2021.
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Bibliography
2021
Eliminating accidental deviations to minimize generalization error and maximize replicability: Applications in connectomics and genomics.
PLoS Comput. Biol., 2021
2008
Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation.
Proceedings of the Design, Automation and Test in Europe, 2008
Efficient techniques for 3-D impedance extraction using mixed boundary element method.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Efficient Direct Boundary Element Method for Resistance Extraction of Substrate With Arbitrary Doping Profile.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
An efficient algorithm for 3-D reluctance extraction considering high frequency effect.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEICE Trans. Electron., 2005
An improved direct boundary element method for substrate coupling resistance extraction.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
A minimum-order boundary element method to extract the 3-D inductance and resistance of the interconnects in VLSI.
Sci. China Ser. F Inf. Sci., 2002
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2001
An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects.
Proceedings of ASP-DAC 2001, 2001
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance.
Proceedings of ASP-DAC 2001, 2001
2000
Hierarchical computation of 3-D interconnect capacitance using direct boundary element method.
Proceedings of ASP-DAC 2000, 2000
A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section.
Proceedings of ASP-DAC 2000, 2000
1999
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1997
Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
A parallel multipole accelerated 3-D capacitance simulator based on an improved model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992