Changhao Yan

According to our database1, Changhao Yan authored at least 43 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis.
ACM Trans. Design Autom. Electr. Syst., 2018

An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. on Circuits and Systems, 2018

Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
Proceedings of the 35th International Conference on Machine Learning, 2018

An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018

A general graph based pessimism reduction framework for design optimization of timing closure.
Proceedings of the 55th Annual Design Automation Conference, 2018

Multi-objective bayesian optimization for analog/RF circuit synthesis.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.
IEEE Trans. VLSI Syst., 2017

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst., 2017

A Novel N-Retry Transactional Memory Model for Multi-Thread Programming.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Layout decomposition for hybrid E-beam and DSA double patterning lithography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Impact of circuit-level non-idealities on vision-based autonomous driving systems.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017

Network flow based cut redistribution and insertion for advanced 1D layout design.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

An efficient algorithm for stencil planning and optimization in E-beam lithography.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A novel unified dummy fill insertion framework with SQP-based optimization method.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst., 2015

Multi-parameter clock skew scheduling.
Integration, 2015

Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method.
Integration, 2015

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks.
SIAM J. Scientific Computing, 2013

An efficient method for gradient-aware dummy fill synthesis.
Integration, 2013

Post-routing layer assignment for double patterning with timing critical paths consideration.
Integration, 2013

Layout decomposition with pairwise coloring for multiple patterning lithography.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays.
IEICE Transactions, 2012

2011
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

A new method for multiparameter robust stability distribution analysis of linear analog circuits.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

An efficient algorithm for multi-domain clock skew scheduling.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method.
IEICE Transactions, 2009

Provably good and practically efficient algorithms for CMP dummy fill.
Proceedings of the 46th Design Automation Conference, 2009

2008
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
Proceedings of the 45th Design Automation Conference, 2008

Efficient techniques for 3-D impedance extraction using mixed boundary element method.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2006
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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