Changhao Yan
Orcid: 0000-0002-8936-3945
According to our database1,
Changhao Yan
authored at least 70 papers
between 2006 and 2024.
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Bibliography
2024
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
2023
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography.
J. Comput. Phys., March, 2023
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions.
SIAM J. Sci. Comput., October, 2022
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble.
CoRR, 2021
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
Proceedings of the 35th International Conference on Machine Learning, 2018
An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018
A general graph based pessimism reduction framework for design optimization of timing closure.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst., 2017
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst., 2015
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method.
Integr., 2015
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2013
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks.
SIAM J. Sci. Comput., 2013
Post-routing layer assignment for double patterning with timing critical paths consideration.
Integr., 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2012
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
A new method for multiparameter robust stability distribution analysis of linear analog circuits.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
Proceedings of the 45th Design Automation Conference, 2008
Efficient techniques for 3-D impedance extraction using mixed boundary element method.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2006
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006