Zuying Luo

According to our database1, Zuying Luo authored at least 31 papers between 2002 and 2021.

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Bibliography

2021
Regression Loss in Transformer-based Supervised Neural Machine Translation.
Int. J. Comput. Commun. Control, 2021

2015
Automatic Facial Expression Analysis of Students in Teaching Environments.
Proceedings of the Biometric Recognition - 10th Chinese Conference, 2015

PS-BloTAM: Pre-sampling based architecture-level temperature analysis methodology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
Accurate architecture-level thermal analysis methods for MPSoC with consideration for leakage power dependence on temperature.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Thermal Analysis with Considering Interactions among Temperature/Power/Heat Conductance and Its Fast Precondition-Solving Algorithm FPSCG.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

2012
Efficient statistical capacitance extraction of nanometer interconnects considering the on-chip line edge roughness.
Microelectron. Reliab., 2012

Localized relaxation theory of circuits and its applications in electro-thermal analyses.
Sci. China Inf. Sci., 2012

Efficient electro-thermal co-analysis on CPU+GPU heterogeneous architecture.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Row-Based Analysis of Structure Power/Ground Grids with General Purpose GPU.
Proceedings of the 12th International Conference on Computer-Aided Design and Computer Graphics, 2011

Comprehensive electro-thermal(ET) analysis with considering ET coupling.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2009
Localized Statistical 3D Thermal Analysis Considering Electro-Thermal Coupling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

FODA: Fast open-defect analysis method for power/ground networks.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

An task scheduling algorithm of real-time leakage power and temperature optimization for MPSoC.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

2008
Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
SN-SOR: Single-Node SOR Method for Statistic Analysis of Power/Ground Networks.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

2006
Power/Ground Network Optimization Considering Decap Leakage Currents.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Time-domain analysis methodology for large-scale RLC circuits and its applications.
Sci. China Ser. F Inf. Sci., 2006

General transistor-level methodology on VLSI low-power design.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.
J. Comput. Sci. Technol., 2005

Vector extraction for average total power estimation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

VLSI on-chip power/ground network optimization considering decap leakage currents.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Leakage Current Estimation of CMOS Circuit with Stack Effect.
J. Comput. Sci. Technol., 2004

Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
Proceedings of the Integrated Circuit and System Design, 2004

Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A maximum total leakage current estimation method.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Partial random walk for large linear network analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications.
Sci. China Ser. F Inf. Sci., 2002

Test Power Optimization Techniques for CMOS Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002


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