Alexandra Ferreron

According to our database, Alexandra Ferreron authored at least 9 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A fault-tolerant last level cache for CMPs operating at ultra-low voltage.

Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera

J. Parallel Distributed Comput., 2019

2018

AISC: Approximate Instruction Set Computer.

Alexandra Ferreron, Jesús Alastruey-Benedé, Darío Suárez Gracia, Ulya R. Karpuzcu

CoRR, 2018

2017

Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications.

Alexandra Ferreron, Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2016

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.

Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Pablo Ibáñez

IEEE Trans. Computers, 2016

Identifying representative regions of parallel HPC applications: a cross-architectural evaluation.

Alexandra Ferreron, Radhika Jagtap, Roxana Rusitoru

Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

2014

Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.

Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera

ACM Trans. Archit. Code Optim., 2014

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.

Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013

Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.

Marta Ortín, Alexandra Ferreron, Jorge Albericio, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals

Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.

Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013