Darío Suárez Gracia

According to our database1, Darío Suárez Gracia authored at least 31 papers between 2007 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2020
Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.
J. Supercomput., 2020

Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.
CoRR, 2020

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files.
IEEE Access, 2020

An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019

Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL.
J. Supercomput., 2019

An Aging-Aware GPU Register File Design Based on Data Redundancy.
IEEE Trans. Computers, 2019

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs.
J. Syst. Archit., 2019

A fault-tolerant last level cache for CMPs operating at ultra-low voltage.
J. Parallel Distributed Comput., 2019


2018
AISC: Approximate Instruction Set Computer.
CoRR, 2018

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR, 2018

Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

2017
Exploiting Data Compression to Mitigate Aging in GPU Register Files.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.
Proceedings of the Parallel Computing is Everywhere, 2017

Abstract Representation of Shared Data for Heterogeneous Computing.
Proceedings of the Languages and Compilers for Parallel Computing, 2017

2016
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.
IEEE Trans. Computers, 2016

Analysis of network-on-chip topologies for cost-efficient chip multiprocessors.
Microprocess. Microsystems, 2016

Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs.
J. Parallel Distributed Comput., 2016

2015
Concurrency in Mobile Browser Engines.
IEEE Pervasive Comput., 2015

2014
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.
ACM Trans. Archit. Code Optim., 2014

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Dynamic construction of circuits for reactive traffic in homogeneous CMPs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Automatic discovery of performance and energy pitfalls in HTML and CSS.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

2009
SigRace: signature-based data race detection.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Light NUCA: A proposal for bridging the inter-cache latency gap.
Proceedings of the Design, Automation and Test in Europe, 2009

2007
A proposal to introduce power and energy notions in computer architecture laboratories.
Proceedings of the 2007 Workshop on Computer Architecture Education, 2007


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