Teresa Monreal Arnal

According to our database, Teresa Monreal Arnal authored at least 23 papers between 1997 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs.

Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Jerónimo Castrillón, Víctor Viñals

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime.

Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals

CoRR, 2022

Forecasting lifetime and performance of a novel NVM last-level cache with compression.

Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals

CoRR, 2022

HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches.

Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, Jerónimo Castrillón

Proceedings of the DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17, 2022

2021

Near-optimal replacement policies for shared caches in multicore processors.

Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José M. Llabería

J. Supercomput., 2021

2019

A fault-tolerant last level cache for CMPs operating at ultra-low voltage.

Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera

J. Parallel Distributed Comput., 2019

ReD: A reuse detector for content selection in exclusive shared last-level caches.

Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals

J. Parallel Distributed Comput., 2019

2018

Reuse Detector: Improving the Management of STT-RAM SLLCs.

Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería

Comput. J., 2018

2016

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.

Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Pablo Ibáñez

IEEE Trans. Computers, 2016

2014

Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.

Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera

ACM Trans. Archit. Code Optim., 2014

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.

Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2012

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors.

Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera

IEEE Trans. Very Large Scale Integr. Syst., 2012

2009

Light NUCA: A proposal for bridging the inter-cache latency gap.

Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.

Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007

Microarchitectural Support for Speculative Register Renaming.

Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Speculative early register release.

Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero

Proceedings of the Third Conference on Computing Frontiers, 2006

2005

Hardware support for early register release.

Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero

Int. J. High Perform. Comput. Netw., 2005

2004

Late Allocation and Early Release of Physical Registers.

Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero

IEEE Trans. Computers, 2004

2002

Hardware Schemes for Early Register Release.

Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero

Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

2000

Dynamic Register Renaming Through Virtual-Physical Registers.

Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals

J. Instr. Level Parallelism, 2000

1999

Delaying Physical Register Allocation through Virtual-Physical Registers.

Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

1997

Virtual registers.

Antonio González, Mateo Valero, José González, Teresa Monreal Arnal

Proceedings of the Fourth International on High-Performance Computing, 1997