Jesús Alastruey-Benedé

According to our database, Jesús Alastruey-Benedé authored at least 21 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code.

Lorién López-Villellas, Carl Christian Kjelgaard Mikkelsen, Juan José Galano-Frutos, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó, Javier Sancho, Pablo García-Risueño

Comput. Phys. Commun., July, 2023

BALANCER: bandwidth allocation and cache partitioning for multicore processors.

Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera

J. Supercomput., June, 2023

Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor.

Rubén Langarita, Adrià Armejach, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó

IEEE ACM Trans. Comput. Biol. Bioinform., 2023

RISC-V for Genome Data Analysis: Opportunities and Challenges.

Lorién López-Villellas, Esteve Pineda-Sánchez, Asaf Badouh, Santiago Marco-Sola, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps.

Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó

IEEE ACM Trans. Comput. Biol. Bioinform., 2022

Berti: an Accurate Local-Delta Data Prefetcher.

Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021

Synchronization Strategies on Many-Core SMT Systems.

Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Maria Carpen-Amarie

Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

2020

Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor.

Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez-Marín, Víctor Viñals Yúfera, Jesús Alastruey-Benedé, Oscar G. Plata

IEEE ACM Trans. Comput. Biol. Bioinform., 2020

Developing an AI IoT application with open software on a RISC-V SoC.

Enrique Torres-Sánchez, Jesús Alastruey-Benedé, Enrique F. Torres Moreno

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019

A fault-tolerant last level cache for CMPs operating at ultra-low voltage.

Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera

J. Parallel Distributed Comput., 2019

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.

Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals

Proceedings of the Workshop on Computer Architecture Education, 2019

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.

Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, Oscar G. Plata

Proceedings of the Data Compression Conference, 2019

2018

AISC: Approximate Instruction Set Computer.

Alexandra Ferreron, Jesús Alastruey-Benedé, Darío Suárez Gracia, Ulya R. Karpuzcu

CoRR, 2018

2016

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.

Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Pablo Ibáñez

IEEE Trans. Computers, 2016

2015

Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints.

Carl Christian Kjelgaard Mikkelsen, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Pablo García-Risueño

Proceedings of the Parallel Processing and Applied Mathematics, 2015

2014

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.

Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013

Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.

Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera

Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2008

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.

Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007

Microarchitectural Support for Speculative Register Renaming.

Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Software Demand, Hardware Supply.

Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals

IEEE Micro, 2006

Speculative early register release.

Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero

Proceedings of the Third Conference on Computing Frontiers, 2006