Jesús Alastruey-Benedé

According to our database1, Jesús Alastruey-Benedé authored at least 12 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2019
A fault-tolerant last level cache for CMPs operating at ultra-low voltage.
J. Parallel Distributed Comput., 2019


Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.
Proceedings of the Data Compression Conference, 2019

2018
AISC: Approximate Instruction Set Computer.
CoRR, 2018

2016
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.
IEEE Trans. Computers, 2016

2015
Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints.
Proceedings of the Parallel Processing and Applied Mathematics, 2015

2014
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2008
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007
Microarchitectural Support for Speculative Register Renaming.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
Software Demand, Hardware Supply.
IEEE Micro, 2006

Speculative early register release.
Proceedings of the Third Conference on Computing Frontiers, 2006


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