Andrew Herdrich

Affiliations:
  • Intel, Santa Clara, CA, USA


According to our database1, Andrew Herdrich authored at least 11 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
RAPID: Enabling fast online policy learning in dynamic public cloud environments.
Neurocomputing, November, 2023

2021
Advances in Microprocessor Cache Architectures Over the Last 25 Years.
IEEE Micro, 2021

LIBRA: Clearing the Cloud Through Dynamic Memory Bandwidth Management.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization.
Proceedings of the 6th IEEE Conference on Network Softwarization, 2020

2017
QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications.
IEEE Syst. J., 2017

2016
Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

CAF: Core to Core Communication Acceleration Framework.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2014
QoS management on heterogeneous architecture for parallel applications.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2012
Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2010
PIRATE: QoS and performance management in CMP architectures.
SIGMETRICS Perform. Evaluation Rev., 2010

2009
Rate-based QoS techniques for cache/memory in CMP platforms.
Proceedings of the 23rd international conference on Supercomputing, 2009


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