Lizhong Chen
Orcid: 0000-0001-5890-7121
According to our database1,
Lizhong Chen
authored at least 51 papers
between 2004 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Neurocomputing, November, 2023
Future Gener. Comput. Syst., August, 2023
Simul-LLM: A Framework for Exploring High-Quality Simultaneous Translation with Large Language Models.
CoRR, 2023
Partitioning-Guided K-Means: Extreme Empty Cluster Resolution for Extreme Model Compression.
CoRR, 2023
Proceedings of the Machine Learning and Knowledge Discovery in Databases: Research Track, 2023
Shiftable Context: Addressing Training-Inference Context Mismatch in Simultaneous Speech Translation.
Proceedings of the International Conference on Machine Learning, 2023
Implicit Memory Transformer for Computationally Efficient Simultaneous Speech Translation.
Proceedings of the Findings of the Association for Computational Linguistics: ACL 2023, 2023
2022
Improving Methodology for Tropical Cyclone Seasonal Forecasting in the Australian and the South Pacific Ocean Regions by Selecting and Averaging Models via Metropolis-Gibbs Sampling.
Remote. Sens., 2022
CoRR, 2022
2020
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01770-4, 2020
UVMBench: A Comprehensive Benchmark Suite for Researching Unified Virtual Memory in GPUs.
CoRR, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020
A Deep Reinforcement Learning Framework for Architectural Exploration: A Routerless NoC Case Study.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
EquiNox: Equivalent NoC Injection Routers for Silicon Interposer-Based Throughput Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework.
CoRR, 2019
Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning.
IEEE Comput. Archit. Lett., 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the ACM International Conference on Supercomputing, 2019
Proceedings of the 48th International Conference on Parallel Processing, 2019
Characterizing On-Chip Traffic Patterns in General-Purpose GPUs: A Deep Learning Approach.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
Tolerating Soft Errors in Deep Learning Accelerators with Reliable On-Chip Memory Designs.
Proceedings of the 2018 IEEE International Conference on Networking, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks.
ACM Trans. Design Autom. Electr. Syst., 2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2016
Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors.
IEEE Trans. Computers, 2016
A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution.
ACM Trans. Archit. Code Optim., 2016
Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator.
J. Parallel Distributed Comput., 2016
Maximizing the performance of NoC-based MPSoCs under total power and power density constraints.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Smart butterfly: reducing static power dissipation of network-on-chip with core-state-awareness.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
Bubble coloring: avoiding routing- and protocol-induced deadlocks with minimal virtual channel requirement.
Proceedings of the International Conference on Supercomputing, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
J. Parallel Distributed Comput., 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
2011
Critical Bubble Scheme: An Efficient Implementation of Globally Aware Network Flow Control.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
2004
Proceedings of the IEEE International Conference on Systems, 2004