Li Zhao

Affiliations:
  • Intel Corporation, Hillsboro, OR, USA
  • University of California, Riverside, CA, USA (PhD)


According to our database1, Li Zhao authored at least 47 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018

2017
QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications.
IEEE Syst. J., 2017

Lightweight Block Cipher Circuits for Automotive and IoT Sensor Devices.
Proceedings of the Hardware and Architectural Support for Security and Privacy, 2017

POSTER: Intrusion Detection System for In-vehicle Networks using Sensor Correlation and Integration.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

2014
QoS management on heterogeneous architecture for parallel applications.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Reducing cache and TLB power by exploiting memory region and privilege level semantics.
J. Syst. Archit., 2013

EMERALD: Characterization of emerging applications and algorithms for low-power devices.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2012
Dynamic QoS management for chip multiprocessors.
ACM Trans. Archit. Code Optim., 2012

Reducing L1 caches power by exploiting software semantics.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

QuickIA: Exploring heterogeneous architectures on real prototypes.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2011
Efficient interaction between OS and architecture in heterogeneous platforms.
ACM SIGOPS Oper. Syst. Rev., 2011

CHOP: Integrating DRAM Caches for CMP Server Platforms.
IEEE Micro, 2011

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs.
J. Parallel Distributed Comput., 2011

HeteroScouts: hardware assist for OS scheduling in heterogeneous CMPs.
Proceedings of the SIGMETRICS 2011, 2011

Cost-effectively offering private buffers in SoCs and CMPs.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

ACCESS: Smart scheduling for asymmetric cache CMPs.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms.
Proceedings of the 48th Design Automation Conference, 2011

2010
Quality of service shared cache management in chip multiprocessor architecture.
ACM Trans. Archit. Code Optim., 2010

Performance characterization and acceleration of Optical Character Recognition on handheld platforms.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

CHOP: Adaptive filter-based DRAM caching for CMP server platforms.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Virtual platform architectures for resource metering in datacenters.
SIGMETRICS Perform. Evaluation Rev., 2009

VM<sup>3</sup>: Measuring, modeling and managing VM shared resources.
Comput. Networks, 2009

Hardware/Software Co-Simulation for Last Level Cache Exploration.
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Frequent value compression in packet-based NoC architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Architecture Support for Improving Bulk Memory Copying and Initialization Performance.
Proceedings of the PACT 2009, 2009

2008
Towards hybrid last level caches for chip-multiprocessors.
SIGARCH Comput. Archit. News, 2008

2007
Hardware Support for Accelerating Data Movement in Server Platform.
IEEE Trans. Computers, 2007

From chaos to QoS: case studies in CMP resource management.
SIGARCH Comput. Archit. News, 2007

Exploring Large-Scale CMP Architectures Using ManySim.
IEEE Micro, 2007

QoS policies and architecture for cache/memory in CMP platforms.
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

A Framework for Providing Quality of Service in Chip Multi-Processors.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Exploring DRAM cache architectures for CMP server platforms.
Proceedings of the 25th International Conference on Computer Design, 2007

Constraint-Aware Large-Scale CMP Cache Design.
Proceedings of the High Performance Computing, 2007

CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
A Network Processor-Based, Content-Aware Switch.
IEEE Micro, 2006

Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Receive Side Coalescing for Accelerating TCP/IP Processing.
Proceedings of the High Performance Computing, 2006

2005
Anatomy and Performance of SSL Processing.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Hardware Support for Bulk Data Movement in Server Platforms.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Design and Implementation of a Content-Aware Switch Using a Network Processor.
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005

SpliceNP: a TCP splicer using a network processor.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005

2004
NePSim: A Network Processor Simulator with a Power Evaluation Framework.
IEEE Micro, 2004

2003
Architectural analysis and instruction-set optimization for design of network protocol processors.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003


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