Antonio Calomarde

Orcid: 0000-0002-4459-8505

According to our database1, Antonio Calomarde authored at least 21 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2023
An automotive case study on the limits of approximation for object detection.
J. Syst. Archit., 2023

2022
Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact.
IEEE Access, 2022

Two examples of approximate arithmetic to reduce hardware complexity and power consumption.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2020
Active Radiation-Hardening Strategy in Bulk FinFETs.
IEEE Access, 2020

2018
Optimization of FinFET-Based Gain Cells for Low Power Sub-<i>V</i> <sub>T</sub> Embedded DRAMs.
J. Low Power Electron., 2018

2017
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
Feasibility of Embedded DRAM Cells on FinFET Technology.
IEEE Trans. Computers, 2016

2015
Variability Influence on FinFET-Based On-Chip Memory Data Paths.
J. Low Power Electron., 2015

2014
All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET.
Microelectron. Reliab., 2014

2013
A single event transient hardening circuit design technique based on strengthening.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Reliability study on technology trends beyond 20nm.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Novel redundant logic design for noisy low voltage scenarios.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
Variation tolerant self-adaptive clock generation architecture based on a ring oscillator.
Proceedings of the IEEE 25th International SOC Conference, 2012

PVTA Tolerant Self-adaptive Clock Generation Architecture.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2011
New redundant logic design concept for high noise and low voltage scenarios.
Microelectron. J., 2011

Analysis of delay mismatching of digital circuits caused by common environmental fluctuations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A new probabilistic design methodology of nanoscale digital circuits.
Proceedings of the CONIELECOMP 2011, 21st International Conference on Electrical, Communications, and Computers, 28 February, 2011

2009
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs.
Microelectron. J., 2009

2006
High level spectral-based analysis of power consumption in DSPs systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Selective Clock-Gating for Low-Power Synchronous Counters.
J. Low Power Electron., 2005


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