Daniel Arumí

IEEE Access, 2023

2022

On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data.

[BibT_eX]

[DOI]

V. Mahboubi

Álvaro Gómez-Pau

Salvador Manich

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021

Simulation of serial RRAM cell based on a Verilog-A compact model.

[BibT_eX]

[DOI]

Juan Bautista Roldán

Mireia Bargallo González

Francesca Campabadal

Liang Fang

Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

Low Cost AES Protection Against DPA Using Rolling Codes.

[BibT_eX]

[DOI]

P. Albiol

Salvador Manich

Álvaro Gómez-Pau

Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020

A forming-free ReRAM cell with low operating voltage.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

2019

Postbond Test of Through-Silicon Vias With Resistive Open Defects.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

2016

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Prebond Testing of Weak Defects in TSVs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

RRAM based cell for hardware security applications.

[BibT_eX]

[DOI]

Salvador Manich

Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

2014

Pre-bond testing of weak defects in TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Post-bond test of Through-Silicon Vias with open defects.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

BIST architecture to detect defects in tsvs during pre-bond testing.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

2011

Gate Leakage Impact on Full Open Defects in Interconnect Lines.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Diagnosis of full open defects in interconnect lines with fan-out.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

2009

Delay caused by resistive opens in interconnecting lines.

[BibT_eX]

[DOI]

Integr., 2009

2008

Experimental Characterization of CMOS Interconnect Open Defects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Full Open Defects in Nanometric CMOS.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Time-dependent Behaviour of Full Open Defects in Interconnect Lines.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Diagnosis of Full Open Defects in Interconnecting Lines.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2005

Defective behaviours of resistive opens in interconnect lines.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

2003

Process-variability aware delay fault testing of ΔV<sub>T</sub> and weak-open defects.

[BibT_eX]

[DOI]

Daniel Arumí-Delgado