Fabio Pavanello

According to our database1, Fabio Pavanello authored at least 16 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Complexity Assessment of Analog Security Primitives Using the Disentropy of Autocorrelation.
CoRR, 2024

2023
Security layers and related services within the Horizon Europe NEUROPULS project.
CoRR, 2023

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023

Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Photonic Convolution Engine Based on Phase-Change Materials and Stochastic Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023


Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Energy efficient on-chip optical broadcast with partial-absorption photodiodes.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

2021
Recent Advances in Photonic Physical Unclonable Functions.
Proceedings of the 26th IEEE European Test Symposium, 2021

2018
Monolithic Optical Transceivers in 65 nm Bulk CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

2017

2016
A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning.
IEEE J. Solid State Circuits, 2016

Depletion-based optical modulators in a bulk 65 nm CMOS platform.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Ultra-efficient CMOS fiber-to-chip grating couplers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

2015
Single-chip microprocessor that communicates directly using light.
Nat., 2015

A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning.
Proceedings of the Symposium on VLSI Circuits, 2015


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