Arnaud Poittevin

According to our database, Arnaud Poittevin authored at least 5 papers between 2020 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.

Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Logic Cell Design and routing Methodology Specific to VNWFET.

Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

2021

Emerging Technologies: Challenges and Opportunities for Logic Synthesis.

Alberto Bosio, Mayeul Cantan, Cédric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020

3D logic cells design and results based on Vertical NWFET technology including tied compact model.

C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu

CoRR, 2020

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.

Chhandak Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020