Guilhem Larrieu

According to our database, Guilhem Larrieu authored at least 8 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.

Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.

Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Logic Cell Design and routing Methodology Specific to VNWFET.

Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

2020

3D logic cells design and results based on Vertical NWFET technology including tied compact model.

C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu

CoRR, 2020

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.

Chhandak Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2018

Pushing the limits of optical information storage using deep learning.

Peter R. Wiecha, Aurélie Lecestre, Nicolas Mallet, Guilhem Larrieu

CoRR, 2018

2017

1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors.

Chhandak Mukherjee, Cristell Maneux, Julien Pezard, Guilhem Larrieu

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2015

Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array.

Guilhem Larrieu, Y. Guerfi, X. L. Han, N. Clement

Proceedings of the 45th European Solid State Device Research Conference, 2015