Daisuke Yamazaki

According to our database1, Daisuke Yamazaki authored at least 9 papers between 2005 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal.
IEEE J. Solid State Circuits, 2022

140 GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS.
Proceedings of the International Conference on IC Design and Technology, 2022

2021
7.6 A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS.
IET Circuits Devices Syst., 2020

2019
A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.
IEICE Electron. Express, 2019

2017
Presentation of contact information of industrial robot's end-effector using vibrotactile sensation.
Proceedings of the 10th International Conference on Human System Interactions, 2017

2007
A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology.
IEEE J. Solid State Circuits, 2007

2006
A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM Technology.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.
IEEE J. Solid State Circuits, 2005


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