Ashkan Beyranvand Nejad

According to our database1, Ashkan Beyranvand Nejad authored at least 15 papers between 2009 and 2015.

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Bibliography

2015
Composable and predictable dynamic loading for time-critical partitioned systems on multiprocessor architectures.
Microprocess. Microsystems, 2015

2014
Composable Virtual Platforms for Mixed-Criticality Embedded Systems.
PhD thesis, 2014

Composable and Predictable Dynamic Loading for Time-Critical Partitioned Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

CoMik: A predictable and cycle-accurately composable real-time microkernel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow.
SIGBED Rev., 2013

A hardware/software platform for QoS bridging over multi-chip NoC-based systems.
Parallel Comput., 2013

A unified execution model for multiple computation models of streaming applications on a composable MPSoC.
J. Syst. Archit., 2013

A software-based technique enabling composable hierarchical preemptive scheduling for time-triggered applications.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

The CompSOC design flow for virtual execution platforms.
Proceedings of the 10th FPGAworld Conference, 2013

2012
Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

Online allocation for contention-free-routing NoCs.
Proceedings of the 2012 Interconnection Network Architecture, 2012

Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints.
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2012

2011
A Unified Execution Model for Data-Driven Applications on a Composable MPSoC.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

An FPGA bridge preserving traffic quality of service for on-chip network-based systems.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
A high-level debug environment for communication-centric debug.
Proceedings of the Design, Automation and Test in Europe, 2009


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