Benny Akesson

According to our database1, Benny Akesson authored at least 68 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of three.

Timeline

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Bibliography

2019
Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets.
ACM Trans. Embedded Comput. Syst., 2019

Uneven memory regulation for scheduling IMA applications on multi-core platforms.
Real-Time Systems, 2019

Response time analysis of multiframe mixed-criticality systems.
Proceedings of the 27th International Conference on Real-Time Networks and Systems, 2019

Memory Bandwidth Regulation for Multiframe Task Sets.
Proceedings of the 25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2019

Towards Continuous Evolution through Automatic Detection and Correction of Service Incompatibilities.
Proceedings of the Joint Proceedings of the Workshop on Model-Driven Engineering for the Internet of Things (MDE4IoT) & of the Workshop on Interplay of Model-Driven and Component-Based Software Engineering (ModComp) Co-located with the IEEE/ACM 22nd International Conference on Model Driven Engineering Languages and Systems (MODELS 2019), 2019

2018
Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements.
IEEE Trans. Computers, 2018

Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact).
DARTS, 2018

Mixed-Criticality Scheduling with Dynamic Memory Bandwidth Regulation.
Proceedings of the 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2018

Pain-mitigation Techniques for Model-based Engineering using Domain-specific Languages.
Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development, 2018

Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers.
Proceedings of the 30th Euromicro Conference on Real-Time Systems, 2018

Mixed-criticality scheduling with memory bandwidth regulation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Reducing the Complexity of Dataflow Graphs Using Slack-Based Merging.
ACM Trans. Design Autom. Electr. Syst., 2017

A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems.
IEEE Trans. Computers, 2017

Combining Dataflow Applications and Real-time Task Sets on Multi-core Platforms.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

Mixed-Criticality Scheduling with Dynamic Redistribution of Shared Cache.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

2016
Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling.
IEEE Trans. Computers, 2016

Architecture and analysis of a dynamically-scheduled real-time memory controller.
Real-Time Systems, 2016

A framework for memory contention analysis in multi-core platforms.
Real-Time Systems, 2016

Scalable and efficient configuration of time-division multiplexed resources.
Journal of Systems and Software, 2016

Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016

Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016

2015
Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation.
ACM Trans. Embedded Comput. Syst., 2015

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels.
ACM Trans. Embedded Comput. Syst., 2015

Certifying execution time in multicores.
Sci. Comput. Program., 2015

T-CREST: Time-predictable multi-core architecture for embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2015

Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC.
Journal of Systems Architecture - Embedded Systems Design, 2015

An efficient configuration methodology for time-division multiplexed single resources.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Mode-controlled data-flow modeling of real-time memory controllers.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs.
ACM Trans. Embedded Comput. Syst., 2014

Unified overhead-aware schedulability analysis for slot-based task-splitting.
Real-Time Systems, 2014

Dynamic Command Scheduling for Real-Time Memory Controllers.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploiting expendable process-margins in DRAMs for run-time performance optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Identifying the sources of unpredictability in COTS-based multicore systems.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Critical-Path-First based allocation of real-time streaming applications on 2D mesh-type multi-cores.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction.
Proceedings of the Practical Aspects of Declarative Languages, 2013

Throughput analysis and Voltage-Frequency Island partitioning for streaming applications under process variation.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

A General Framework for Average-Case Performance Analysis of Shared Resources.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Bounding SDRAM interference: detailed analysis vs. latency-rate analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

Conservative open-page policy for mixed time-criticality memory controllers.
Proceedings of the Design, Automation and Test in Europe, 2013

Architecture and optimal configuration of a real-time multi-channel memory controller.
Proceedings of the Design, Automation and Test in Europe, 2013

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013

Towards variation-aware system-level power estimation of DRAMs: an empirical approach.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A reconfigurable real-time SDRAM controller for mixed time-criticality systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Power versus quality trade-offs for adaptive real-time applications.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

A Predictor-Based Power-Saving Policy for DRAM Memories.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Memory-map selection for firm real-time SDRAM controllers.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DRAM selection and configuration for real-time mobile systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Run-time power-down strategies for real-time SDRAM memory controllers.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Automatic Generation of Efficient Predictable Memory Patterns.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Improved Power Modeling of DDR SDRAMs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Architectures and modeling of predictable memory controllers for improved system integration.
Proceedings of the Design, Automation and Test in Europe, 2011

Designing next-generation real-time streaming systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Composability and Predictability for Independent Application Development, Verification, and Execution.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Classification and Analysis of Predictable Memory Patterns.
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010

2009
Multi-processor programming in the embedded system curriculum.
SIGBED Review, 2009

Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Composable Resource Sharing Based on Latency-Rate Servers.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008

2007
Predator: a predictable SDRAM memory controller.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007


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