Athanasios Ramkaj

According to our database, Athanasios Ramkaj authored at least 11 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 1024-Channel 268-nW/Pixel 36×36 μm²/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.

Moon Hyung Jang, Maddy Hays, Wei-Han Yu, Changuk Lee, Pietro Caragiulo, Athanasios T. Ramkaj, Pingyu Wang, A. J. Phillips, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E. J. Chichilnisky, Boris Murmann, Dante G. Muratore

IEEE J. Solid State Circuits, April, 2024

2023

High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design.

Athanasios Ramkaj, Michael Perrott, Baher Haroun, Boris Murmann

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Multi-Gigahertz Nyquist Analog-to-Digital Converters - Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies, 3

Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

Springer, ISBN: 978-3-031-22708-0, 2023

2022

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity.

Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET.

Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 56 GS/s 8-bit 0.011 mm² 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS.

Pietro Caragiulo, Athanasios Ramkaj, Amin Arbabian, Boris Murmann

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2020

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.

Athanasios T. Ramkaj, Juan Carlos Pena Ramos, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Marian Verhelst, Filip Tavernier

IEEE J. Solid State Circuits, 2020

2019

A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS.

Athanasios Ramkaj, Juan Carlos Pena Ramos, Yifan Lyu, Maarten Strackx, Marcel J. M. Pelgrom, Michiel Steyaert, Marian Verhelst, Filip Tavernier

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS.

Athanasios T. Ramkaj, Michiel S. J. Steyaert, Filip Tavernier

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS.

Athanasios Ramkaj, Maarten Strackx, Michiel S. J. Steyaert, Filip Tavernier

IEEE J. Solid State Circuits, 2018

2017

A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS.

Athanasios Ramkaj, Maarten Strackx, Michiel Steyaert, Filip Tavernier

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017