Basel Halak

Orcid: 0000-0003-3470-7226

According to our database1, Basel Halak authored at least 76 papers between 2008 and 2024.

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Bibliography

2024
DL2Fence: Integrating Deep Learning and Frame Fusion for Enhanced Detection and Localization of Refined Denial-of-Service in Large-Scale NoCs.
CoRR, 2024

Evaluation of Performance, Energy, and Computation Costs of Quantum-Attack Resilient Encryption Algorithms for Embedded Devices.
IEEE Access, 2024

2023
Software supply chain: review of attacks, risk assessment strategies and security controls.
CoRR, 2023

Cascaded Machine Learning Model Based DoS Attacks Detection and Classification in NoC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Methodology for Cybersecurity Risk Assessment in Supply Chains.
Proceedings of the Computer Security. ESORICS 2023 International Workshops, 2023

A PUF Based on the Non-Linearity of Memristors.
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023

Hardware Trojan Detection and High-Precision Localization in NoC-Based MPSoC Using Machine Learning.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Tamper Resistant Design of Convolutional Neural Network Hardware Accelerator.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022
A Tutorial on Adversarial Learning Attacks and Countermeasures.
CoRR, 2022

CIST: A Serious Game for Hardware Supply Chain.
Comput. Secur., 2022

Comments and Corrections Correction to "Comparative Analysis of Energy Costs of Asymmetric vs Symmetric Encryption-Based Security Applications".
IEEE Access, 2022

Comparative Analysis of Energy Costs of Asymmetric vs Symmetric Encryption-Based Security Applications.
IEEE Access, 2022

Toward Autonomous Physical Security Defenses Using Machine Learning.
IEEE Access, 2022

Towards Hardware Trojan Resilient Design of Convolutional Neural Networks.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

2021
ARMOR: An Anti-Counterfeit Security Mechanism for Low Cost Radio Frequency Identification Systems.
IEEE Trans. Emerg. Top. Comput., 2021

Learning-based BTI stress estimation and mitigation in multi-core processor systems.
Microprocess. Microsystems, 2021

ASSURE: A Hardware-Based Security Protocol for Resource-Constrained IoT Systems.
J. Hardw. Syst. Secur., 2021

A Survey on the Susceptibility of PUFs to Invasive, Semi-Invasive and Noninvasive Attacks: Challenges and Opportunities for Future Directions.
J. Circuits Syst. Comput., 2021

Anti-BlUFf: towards counterfeit mitigation in IC supply chains using blockchain and PUF.
Int. J. Inf. Sec., 2021

MOTENS: A Pedagogical Design Model for Serious Cyber Games.
CoRR, 2021

2020
Bootstrapped Driver and the Single-Event-Upset Effect.
IEEE Trans. Circuits Syst., 2020

On the Design and Analysis of a Biometric Authentication System Using Keystroke Dynamics.
Cryptogr., 2020

Cube Attack on a Trojan-Compromised Hardware Implementation of Ascon.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

On the Integration of Physically Unclonable Functions into ARM TrustZone Security Technology.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
A reliable PUF in a dual function SRAM.
Integr., 2019

VLSI Implementation of a Fully-Pipelined K-Best MIMO Detector with Successive Interference Cancellation.
Circuits Syst. Signal Process., 2019

Towards a Supply Chain Management System for Counterfeit Mitigation using Blockchain and PUF.
CoRR, 2019

Using Hardware Performance Counters to Detect Control Hijacking Attacks.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

A Two-Flights Mutual Authentication for Energy-Constrained IoT Devices.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

Two-Stage Architectures for Resilient Lightweight PUFs.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

On the Encryption of the Challenge in Physically Unclonable Functions.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
Lifetime Reliability-Aware Digital Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Multi-Path Aging Sensor for Cost-Efficient Delay Fault Prediction.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Hardware Efficient Architecture for Element-Based Lattice Reduction Aided K-Best Detector for MIMO Systems.
J. Sens. Actuator Networks, 2018

Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Lightweight PUF-Based Authentication Protocol for IoT Devices.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Early detection of system-level anomalous behaviour using hardware performance counters.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cost-efficient design for modeling attacks resistant PUFs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cell Flipping with Distributed Refresh for Cache Ageing Minimization.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
BTI mitigation by anti-ageing software patterns.
Microelectron. Reliab., 2017

Course on secure hardware design of silicon chips.
IET Circuits Devices Syst., 2017

A Secure and Private Billing Protocol for Smart Metering.
IACR Cryptol. ePrint Arch., 2017

Performance Analysis of Secure and Private Billing Protocols for Smart Metering.
Cryptogr., 2017

An ageing-aware digital synthesis approach.
Proceedings of the 14th International Conference on Synthesis, 2017

Lightweight obfuscation techniques for modeling attacks resistant PUFs.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Hardware performance counters for system reliability monitoring.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

A cost-efficient delay-fault monitor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2016

The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology.
Microelectron. Reliab., 2016

A Survey of Hardware Implementations of Elliptic Curve Cryptographic Systems.
IACR Cryptol. ePrint Arch., 2016

A Survey of VLSI Implementations of Tree Search Algorithms for MIMO Detection.
Circuits Syst. Signal Process., 2016

Modified Micropipline Architecture for Synthesizable Asynchronous FIR Filter Design.
CoRR, 2016

Secure communication interface design for IoT applications using the GSM network.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Overview of PUF-based hardware security solutions for the internet of things.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

NBTI aging evaluation of PUF-based differential architectures.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Analysis of BTI aging of level shifters.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Energy efficient bootstrapped CMOS inverter for ultra-low power applications.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Design and evaluation of a system-on-a-chip course.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

Plagiarism detection and prevention techniques in engineering education.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator.
Proceedings of the 21th IEEE European Test Symposium, 2016

Ageing Impact on a High Speed Voltage Comparator with Hysteresis.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

NBTI Lifetime Evaluation and Extension in Instruction Caches.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

Static Aging Analysis Using 3-Dimensional Delay Library.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

2015
VLSI implementation of a scalable K-best MIMO detector.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

Area efficient configurable physical unclonable functions for FPGAs identification.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A dynamic CDMA network for multicore systems.
Microelectron. J., 2014

Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation.
IET Comput. Digit. Tech., 2014

A low-cost radiation hardened flip-flop.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Power Balanced Circuits for Leakage-Power-Attacks Resilient Design.
IACR Cryptol. ePrint Arch., 2013

2012
Self-Timed Physically Unclonable Functions.
Proceedings of the 5th International Conference on New Technologies, 2012

2011
Statistical analysis of crosstalk-induced errors for on-chip interconnects.
IET Comput. Digit. Tech., 2011

2010
Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2008
Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels.
IEEE Trans. Computers, 2008

The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods.
Proceedings of the Design, Automation and Test in Europe, 2008


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