Vasileios Tenentes

Orcid: 0000-0002-3980-3746

According to our database1, Vasileios Tenentes authored at least 43 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Multi-Vt-Based Energy Efficiency Optimization for ASIC Designs of the Double Secure Hash Algorithm Toward a Sustainable Bitcoin Network.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Evaluating Trusted Firmware Remote Attestation on ARM and RISC-V Edge Computing Prototypes.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

2023
Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain.
Proceedings of the 8th South-East Europe Design Automation, 2023

Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures.
Proceedings of the 8th South-East Europe Design Automation, 2023

MetaSPICE: Metaprogramming SPICE Framework for the Design Space Exploration of PUF Circuits.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs.
Proceedings of the IEEE European Test Symposium, 2023

High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications.
Proceedings of the IEEE European Test Symposium, 2023

2022
REVOLVER: A Zero-Step Execution Emulation Framework for Mitigating Power Side-Channel Attacks on ARM64.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

2021
Energy Efficient Speech Command Recognition for Private Smart Home IoT Applications.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

2019
Run-time Detection and Mitigation of Power-Noise Viruses.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Collective-Aware System-on-Chips for Dependable IoT Applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Recycled IC detection through aging sensor.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Aging Benefits in Nanometer CMOS Designs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance.
J. Electron. Test., 2017

Online tuning of Dynamic Power Management for efficient execution of interactive workloads.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Low power probabilistic online monitoring of systematic erroneous behaviour.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Hardware and software innovations in energy-efficient system-reliability monitoring.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Low cost error monitoring for improved maintainability of IoT applications.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Reliable Power Gating With NBTI Aging Benefits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology.
Microelectron. Reliab., 2016

Susceptible workload driven selective fault tolerance using a probabilistic fault model.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

BTI aware thermal management for reliable DVFS designs.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

BTI and leakage aware dynamic voltage scaling for reliable low power cache memories.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Diagnosis of power switches with power-distribution-network consideration.
Proceedings of the 20th IEEE European Test Symposium, 2015

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
High Quality Testing of Grid Style Power Gating.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Embedded testing architectures
PhD thesis, 2013

High-Quality Statistical Test Compression With Narrow ATE Interface.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2011
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Low Power Test-Compression for High Test-Quality and Low Test-Data Volume.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Self-Freeze Linear Decompressors for Low Power Testing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Defect aware X-filling for low-power scan testing.
Proceedings of the Design, Automation and Test in Europe, 2010

Defect Coverage-Driven Window-Based Test Compression.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2008
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores.
Proceedings of the Design, Automation and Test in Europe, 2008


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