Giorgio Di Natale

According to our database1, Giorgio Di Natale authored at least 135 papers between 2000 and 2018.

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Bibliography

2018
Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era.
IEEE Trans. Emerging Topics Comput., 2018

Towards a Dependable True Random Number Generator With Self-Repair Capabilities.
IEEE Trans. on Circuits and Systems, 2018

A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions.
IEEE Trans. on Circuits and Systems, 2018

Assessing body built-in current sensors for detection of multiple transient faults.
Microelectronics Reliability, 2018

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead.
IEEE Design & Test, 2018

Encryption of test data: which cipher is better?
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A New Secure Stream Cipher for Scan Chain Encryption.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

SI ECCS: SECure context saving for IoT devices.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017
Computing reliability: On the differences between software testing and software fault injection techniques.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Report on DATE 2017 in Lausanne.
IEEE Design & Test, 2017

Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Experimentations on scan chain encryption with PRESENT.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Hacking the Control Flow error detection mechanism.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Reliability of computing systems: From flip flops to variables.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Scan chain encryption for the test, diagnosis and debug of secure circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Do we need a holistic approach for the design of secure IoT systems?
Proceedings of the Computing Frontiers Conference, 2017

2016
Editorial.
IEEE Trans. Emerging Topics Comput., 2016

Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE).
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Ring oscillators analysis for security purposes in Spartan-6 FPGAs.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.
JETC, 2016

Frontside Versus Backside Laser Injection: A Comparative Study.
JETC, 2016

Security primitives (PUF and TRNG) with STT-MRAM.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Cache- and register-aware system reliability evaluation based on data lifetime analysis.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Faster-than-at-speed execution of functional programs: An experimental analysis.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Using outliers to detect stealthy hardware trojan triggering?
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Cross-layer system reliability assessment framework for hardware faults.
Proceedings of the 2016 IEEE International Test Conference, 2016

Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Cache-aware reliability evaluation through LLVM-based analysis and fault injection.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

ETS 2016 foreword.
Proceedings of the 21th IEEE European Test Symposium, 2016

SEcube™: An open-source security platform in a single SoC.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

System-level reliability evaluation through cache-aware software-based fault injection.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Towards a highly reliable SRAM-based PUFs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

STT-MRAM-Based Strong PUF Architecture.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Digital Right Management for IP Protection.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

3D DFT Challenges and Solutions.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Challenges in designing trustworthy cryptographic co-processors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Session-less based thermal-aware 3D-SIC test scheduling.
Proceedings of the 20th IEEE European Test Symposium, 2015

Hardware Trojan prevention using layout-level design approach.
Proceedings of the European Conference on Circuit Theory and Design, 2015

DTIS 2015 foreword.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

STT MRAM-Based PUFs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

New testing procedure for finding insertion sites of stealthy hardware trojans.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison.
IEEE Trans. VLSI Syst., 2014

Test Versus Security: Past and Present.
IEEE Trans. Emerging Topics Comput., 2014

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS.
Microelectronics Reliability, 2014

Testing Methods for PUF-Based Secure Key Storage Circuits.
J. Electronic Testing, 2014

Built-in self-test for manufacturing TSV defects before bonding.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014



Fault injection tools based on Virtual Machines.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Customized cell detector for laser-induced-fault detection.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Cross-layer early reliability evaluation: Challenges and promises.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A novel adaptive fault tolerant flip-flop architecture based on TMR.
Proceedings of the 19th IEEE European Test Symposium, 2014

DTIS 2014 foreword.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Layout-aware laser fault injection simulation and modeling: From physical level to gate level.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

A survey on simulation-based fault injection tools for complex systems.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Laser attacks on integrated circuits: From CMOS to FD-SOI.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Hacking and protecting IC hardware.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Testing PUF-based secure key storage circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A novel differential scan attack on advanced DFT structures.
ACM Trans. Design Autom. Electr. Syst., 2013

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection.
Microelectronics Reliability, 2013

TRUDEVICE: A COST Action on Trustworthy Manufacturing and Utilization of Secure Devices.
Information Security Journal: A Global Perspective, 2013

Multilevel Ionizing-Induced Transient Fault Simulator.
Information Security Journal: A Global Perspective, 2013

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis.
Information Security Journal: A Global Perspective, 2013

Secure JTAG Implementation Using Schnorr Protocol.
J. Electronic Testing, 2013

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic.
J. Electronic Testing, 2013

A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A 3D IC BIST for pre-bond test of TSVs using ring oscillators.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A smart test controller for scan chains in secure circuits.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

A BIST method for TSVs pre-bond test.
Proceedings of the 8th International Design and Test Symposium, 2013

A bulk built-in sensor for detection of fault attacks.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Laser-Induced Fault Simulation.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
On Countermeasures Against Fault Attacks on the Advanced Encryption Standard.
Proceedings of the Fault Analysis in Cryptography, 2012

Statistical Reliability Estimation of Microprocessor-Based Systems.
IEEE Trans. Computers, 2012

Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode.
Microelectronics Reliability, 2012

Scan attacks on side-channel and fault attack resistant public-key implementations.
J. Cryptographic Engineering, 2012

Are advanced DfT structures sufficient for preventing scan-attacks?
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On-chip test comparison for protecting confidential data in secure ICs.
Proceedings of the 17th IEEE European Test Symposium, 2012

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A New Scan Attack on RSA in Presence of Industrial Countermeasures.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011
New security threats against chips containing scan chain structures.
Proceedings of the HOST 2011, 2011

Scan Attacks and Countermeasures in Presence of Scan Response Compactors.
Proceedings of the 16th European Test Symposium, 2011

A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Power consumption traces realignment to improve differential power analysis.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Self-Test Techniques for Crypto-Devices.
IEEE Trans. VLSI Syst., 2010

Evaluation of concurrent error detection techniques on the advanced encryption standard.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Evaluation of concurrent error detection techniques on the Advanced Encryption Standard.
Proceedings of the 15th European Test Symposium, 2010

Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Ensuring high testability without degrading security: Embedded tutorial on "test and security".
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard.
J. Electronic Testing, 2009

2008
March Test Generation Revealed.
IEEE Trans. Computers, 2008

A Modular Memory BIST for Optimized Memory Repair.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Reliable Architecture for the Advanced Encryption Standard.
Proceedings of the 13th European Test Symposium, 2008

An Integrated Validation Environment for Differential Power Analysis.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

On-Line Instruction-Checking in Pipelined Microprocessors.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

LIFTING: A Flexible Open-Source Fault Simulator.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.
IET Computers & Digital Techniques, 2007

A Dependable Parallel Architecture for SBoxes.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

An On-Line Fault Detection Scheme for SBoxes in Secure Circuits.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A Novel Parity Bit Scheme for SBox in AES Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Single-Event Upset Analysis and Protection in High Speed Circuits.
Proceedings of the 11th European Test Symposium, 2006

A 22n March Test for Realistic Static Linked Faults in SRAMs.
Proceedings of the 11th European Test Symposium, 2006

Automatic March Tests Generation for Multi-Port SRAMs.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Automatic march tests generations for static linked faults in SRAMs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
March AB, March AB1: new March tests for unlinked dynamic memory faults.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Automatic March tests generation for static and dynamic faults in SRAMs.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

2003
Online Self-Repair of FIR Filters.
IEEE Design & Test of Computers, 2003

Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.
IEEE Communications Magazine, 2003

Data Critically Estimation In Software Applications.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAUST: FAUlt-injection Script-based Tool.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A Watchdog Processor to Detect Data and Control Flow Errors.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
An on-line BIST RAM architecture with self-repair capabilities.
IEEE Trans. Reliability, 2002

Static Analysis of SEU Effects on Software Applications.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

An Optimal Algorithm for the Automatic Generation of March Tests.
Proceedings of the 2002 Design, 2002

Specification and Design of a New Memory Fault Simulator.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Online and Offline BIST in IP-Core Design.
IEEE Design & Test of Computers, 2001

GRAAL: a tool for highly dependable SRAMs generation.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Validation of a Software Dependability Tool via Fault Injection Experiments.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

SEU effect analysis in an open-source router via a distributed fault injection environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Control-Flow Checking via Regular Expressions.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Memory Read Faults: Taxonomy and Automatic Test Generation.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
A programmable BIST architecture for clusters of multiple-port SRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A Family of Self-Repair SRAM Cores.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000


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