Richard Wong

According to our database1, Richard Wong authored at least 33 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer.
J. Solid-State Circuits, 2019

Study of proton radiation effect to row hammer fault in DDR4 SDRAMs.
Microelectronics Reliability, 2018

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree.
Microelectronics Reliability, 2018

A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

BPPT - Bulk potential protection technique for hardened sequentials.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

IZIP: In-place zero overhead interconnect protection via PIP redundancy.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Rectifeye: a vision-correcting system for virtual reality.
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - VR Showcase, 2016

Rectifeye: a vision-correcting system for virtual reality.
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Posters, 2016

NBTI Lifetime Evaluation and Extension in Instruction Caches.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

New insights into the impact of SEUs in FPGA CRAMs.
IEICE Electronic Express, 2015

Terrestrial SER characterization for nanoscale technologies: A comparative study.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Analysis of advanced circuits for SET measurement.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Single Event Resilient Dynamic Logic Designs.
J. Electronic Testing, 2014

Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser.
J. Electronic Testing, 2014

New approaches for synthesis of redundant combinatorial logic for selective fault tolerance.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Correlation of Heavy-Ion and Laser Testing on a DC/DC PWM Controller.
J. Electronic Testing, 2013

Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Placement of repair circuits for in-field FPGA repair.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Networking industry trends in ESD protection for high speed IOs.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.
IEEE Trans. on Circuits and Systems, 2012

Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter.
J. Electronic Testing, 2012

Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Mitigating the effects of large multiple cell upsets (MCUs) in memories.
ACM Trans. Design Autom. Electr. Syst., 2011

Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS.
J. Solid-State Circuits, 2011

Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS.
Proceedings of the 16th European Test Symposium, 2011

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals.
IEEE Trans. on Circuits and Systems, 2010

Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A parallel sort-balance mutual range-join algorithm on hypercube computers.
Microprocessors and Microsystems - Embedded Hardware Design, 1998