Biwei Xie

Orcid: 0000-0003-4045-6806

According to our database1, Biwei Xie authored at least 37 papers between 2015 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
AiLO: A Predictive Framework for Logic Optimization Using Multi-Scale Cross-Attention Transformer.
ACM Trans. Design Autom. Electr. Syst., July, 2026

AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing.
ACM Trans. Design Autom. Electr. Syst., May, 2026

FAST: Failure-Aware Asynchronous Search with Early Termination for Physical Design.
Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

GNN-Based Timing Yield Prediction From Statistical Static Timing Analysis.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Bounded Dynamic Level Maintenance for Efficient Logic Optimization.
CoRR, December, 2025

BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction.
CoRR, November, 2025

OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2025

An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph Extraction.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Toward Advancing 3D-ICs Physical Design: Challenges and Opportunities.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

ACLP: Towards More Accurate Loop Prediction for Execution Efficiency in High-Performance Processors.
Proceedings of the Advanced Parallel Processing Technologies, 2025

2024
QR-DeepONet: resolve abnormal convergence issue in deep operator network.
Mach. Learn. Sci. Technol., 2024

Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network.
CoRR, 2024

Enhancing ASIC Technology Mapping via Parallel Supergate Computing.
CoRR, 2024

Instance-level Timing Learning and Prediction at Placement using Res-UNet Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Parallel AIG Refactoring via Conflict Breaking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Simultaneous Conjugate Gradient and iAFF-UNet for Accurate IR Drop Calculation.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

Net Resource Allocation: A Desirable Initial Routing Step.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

iPD: An Open-source intelligent Physical Design Toolchain.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

iEDA: An Open-source infrastructure of EDA.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA.
CoRR, 2023

iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library.
CoRR, 2023

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

iPL-3D: A Novel Bilevel Programming Model for Die-to-Die Placement.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance Extraction.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
High fusion computers: The IoTs, edges, data centers, and humans-in-the-loop as a computer.
CoRR, 2022

Exploiting Architecture Advances for Sparse Solvers in Circuit Simulation.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2018
Big Data Dwarfs: Towards Fully Understanding Big Data Analytics Workloads.
CoRR, 2018

Cymbalo: An Efficient Graph Processing Framework for Machine Learning.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

Towards Efficient SpMV on Sunway Manycore Architectures.
Proceedings of the 32nd International Conference on Supercomputing, 2018

CVR: efficient vectorization of SpMV on x86 processors.
Proceedings of the 2018 International Symposium on Code Generation and Optimization, 2018

Benchmarking SpMV Methods on Many-Core Platforms.
Proceedings of the Benchmarking, Measuring, and Optimizing, 2018

AIBench: Towards Scalable and Comprehensive Datacenter AI Benchmarking.
Proceedings of the Benchmarking, Measuring, and Optimizing, 2018

Data motifs: a lens towards fully understanding big data and AI workloads.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
A Dwarf-based Scalable Big Data Benchmarking Methodology.
CoRR, 2017

2016
Understanding Data Analytics Workloads on Intel(R) Xeon Phi(R).
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

2015
Characterizing Data Analytics Workloads on Intel Xeon Phi.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015


  Loading...