Bo Zhang
Orcid: 0000-0003-3603-6016Affiliations:
- Columbia University, Department of Electrical Engineering, NY, USA (PhD 2023)
According to our database1,
Bo Zhang authored at least 16 papers
between 2021 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
AACIM: A 2785-TOPS/W, 161-TOP/mm<sup>2</sup>, <1.17%-RMSE, Analog-In Analog-Out Computing-In-Memory Macro in 28 nm.
IEEE J. Solid State Circuits, June, 2026
2025
IEEE J. Solid State Circuits, May, 2025
2024
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks.
IEEE J. Solid State Circuits, June, 2024
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm.
IEEE J. Solid State Circuits, March, 2024
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, February, 2024
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core.
IEEE J. Solid State Circuits, February, 2024
Proceedings of the 30th Annual International Conference on Mobile Computing and Networking, 2024
A 1-TFLOPS/W, 28-nm Deep Neural Network Accelerator Featuring Online Compression and Decompression and BF16 Digital In-Memory-Computing Hardware.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits, May, 2023
Proceedings of the ACM SIGCOMM 2023 Conference, 2023
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021